Lines Matching +full:redistributor +full:- +full:stride
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
86 compatible = "arm,cortex-a57";
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
216 cluster1_l2: l2-cache1 {
220 cluster2_l2: l2-cache2 {
224 cluster3_l2: l2-cache3 {
229 gic: interrupt-controller@4d000000 {
230 compatible = "arm,gic-v3";
231 #interrupt-cells = <3>;
232 #address-cells = <2>;
233 #size-cells = <2>;
235 interrupt-controller;
236 #redistributor-regions = <1>;
237 redistributor-stride = <0x0 0x30000>;
245 its_dsa: interrupt-controller@c6000000 {
246 compatible = "arm,gic-v3-its";
247 msi-controller;
248 #msi-cells = <1>;
254 compatible = "arm,armv8-timer";
262 compatible = "arm,cortex-a57-pmu";
267 compatible = "hisilicon,mbigen-v2";
271 msi-parent = <&its_dsa 0x40080>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 num-pins = <2>;
278 msi-parent = <&its_dsa 0x40000>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 num-pins = <128>;
285 msi-parent = <&its_dsa 0x40040>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 num-pins = <128>;
292 msi-parent = <&its_dsa 0x40085>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 num-pins = <10>;
300 compatible = "hisilicon,mbigen-v2";
304 msi-parent = <&its_dsa 0x40800>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 num-pins = <409>;
310 mbigen_sas0: intc-sas0 {
311 msi-parent = <&its_dsa 0x40900>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 num-pins = <128>;
330 * when iommu-map entry is used along with the PCIe node.
331 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
334 compatible = "arm,smmu-v3";
336 #iommu-cells = <1>;
337 dma-coherent;
338 smmu-cb-memtype = <0x0 0x1>;
339 hisilicon,broken-prefetch-cmd;
344 compatible = "simple-bus";
345 #address-cells = <2>;
346 #size-cells = <2>;
350 compatible = "hisilicon,hip06-lpc";
351 #size-cells = <1>;
352 #address-cells = <2>;
356 compatible = "ipmi-bt";
362 uart0: lpc-uart@2f8 {
364 clock-frequency = <1843200>;
371 compatible = "fixed-clock";
372 clock-frequency = <50000000>;
373 #clock-cells = <0>;
377 compatible = "generic-ohci";
379 interrupt-parent = <&mbigen_usb>;
381 dma-coherent;
386 compatible = "generic-ehci";
388 interrupt-parent = <&mbigen_usb>;
390 dma-coherent;
395 compatible = "hisilicon,peri-subctrl","syscon";
400 compatible = "hisilicon,dsa-subctrl", "syscon";
405 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
415 compatible = "hisilicon,hns-mdio";
417 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
418 #address-cells = <1>;
419 #size-cells = <0>;
421 phy0: ethernet-phy@0 {
422 compatible = "ethernet-phy-ieee802.3-c22";
426 phy1: ethernet-phy@1 {
427 compatible = "ethernet-phy-ieee802.3-c22";
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "hisilicon,hns-dsaf-v2";
436 mode = "6port-16rss";
439 reg-names = "ppe-base", "dsaf-base";
440 interrupt-parent = <&mbigen_dsaf0>;
441 subctrl-syscon = <&dsa_subctrl>;
442 reset-field-offset = <0>;
527 desc-num = <0x400>;
528 buf-size = <0x1000>;
529 dma-coherent;
533 serdes-syscon = <&serdes_ctrl>;
534 port-rst-offset = <0>;
535 port-mode-offset = <0>;
536 media-type = "fiber";
541 serdes-syscon= <&serdes_ctrl>;
542 port-rst-offset = <1>;
543 port-mode-offset = <1>;
544 media-type = "fiber";
549 phy-handle = <&phy0>;
550 serdes-syscon= <&serdes_ctrl>;
551 port-rst-offset = <4>;
552 port-mode-offset = <2>;
553 media-type = "copper";
558 phy-handle = <&phy1>;
559 serdes-syscon= <&serdes_ctrl>;
560 port-rst-offset = <5>;
561 port-mode-offset = <3>;
562 media-type = "copper";
566 eth0: ethernet-4{
567 compatible = "hisilicon,hns-nic-v2";
568 ae-handle = <&dsaf0>;
569 port-idx-in-ae = <4>;
570 local-mac-address = [00 00 00 00 00 00];
572 dma-coherent;
575 eth1: ethernet-5{
576 compatible = "hisilicon,hns-nic-v2";
577 ae-handle = <&dsaf0>;
578 port-idx-in-ae = <5>;
579 local-mac-address = [00 00 00 00 00 00];
581 dma-coherent;
584 eth2: ethernet-0{
585 compatible = "hisilicon,hns-nic-v2";
586 ae-handle = <&dsaf0>;
587 port-idx-in-ae = <0>;
588 local-mac-address = [00 00 00 00 00 00];
590 dma-coherent;
593 eth3: ethernet-1{
594 compatible = "hisilicon,hns-nic-v2";
595 ae-handle = <&dsaf0>;
596 port-idx-in-ae = <1>;
597 local-mac-address = [00 00 00 00 00 00];
599 dma-coherent;
603 compatible = "hisilicon,hip06-sas-v2";
605 sas-addr = [50 01 88 20 16 00 00 00];
606 hisilicon,sas-syscon = <&dsa_subctrl>;
607 ctrl-reset-reg = <0xa60>;
608 ctrl-reset-sts-reg = <0x5a30>;
609 ctrl-clock-ena-reg = <0x338>;
611 queue-count = <16>;
612 phy-count = <8>;
613 dma-coherent;
614 interrupt-parent = <&mbigen_sas0>;
645 compatible = "hisilicon,hip06-sas-v2";
647 sas-addr = [50 01 88 20 16 00 00 00];
648 hisilicon,sas-syscon = <&pcie_subctl>;
649 hip06-sas-v2-quirk-amt;
650 ctrl-reset-reg = <0xa18>;
651 ctrl-reset-sts-reg = <0x5a0c>;
652 ctrl-clock-ena-reg = <0x318>;
654 queue-count = <16>;
655 phy-count = <8>;
656 dma-coherent;
657 interrupt-parent = <&mbigen_sas1>;
688 compatible = "hisilicon,hip06-sas-v2";
690 sas-addr = [50 01 88 20 16 00 00 00];
691 hisilicon,sas-syscon = <&pcie_subctl>;
692 ctrl-reset-reg = <0xae0>;
693 ctrl-reset-sts-reg = <0x5a70>;
694 ctrl-clock-ena-reg = <0x3a8>;
696 queue-count = <16>;
697 phy-count = <9>;
698 dma-coherent;
699 interrupt-parent = <&mbigen_sas2>;
730 compatible = "hisilicon,hip06-pcie-ecam";
733 bus-range = <0 31>;
734 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
735 msi-map-mask = <0xffff>;
736 #address-cells = <3>;
737 #size-cells = <2>;
739 dma-coherent;
743 #interrupt-cells = <1>;
744 interrupt-map-mask = <0xf800 0 0 7>;
745 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4