Lines Matching +full:bus +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <2>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a53";
33 enable-method = "psci";
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
44 compatible = "arm,cortex-a53";
47 enable-method = "psci";
51 compatible = "arm,cortex-a53";
54 enable-method = "psci";
58 gic: interrupt-controller@f1001000 {
59 compatible = "arm,gic-400";
62 #address-cells = <0>;
63 #interrupt-cells = <3>;
64 interrupt-controller;
68 compatible = "arm,armv8-timer";
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
85 crg: clock-reset-controller@8a22000 {
86 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
88 #clock-cells = <1>;
89 #reset-cells = <2>;
91 gmacphyrst: reset-controller {
92 compatible = "ti,syscon-reset";
93 #reset-cells = <1>;
94 ti,reset-bits =
102 sysctrl: system-controller@8000000 {
103 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
105 #clock-cells = <1>;
106 #reset-cells = <2>;
109 perictrl: peripheral-controller@8a20000 {
110 compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
111 "simple-mfd";
113 #address-cells = <1>;
114 #size-cells = <1>;
117 usb2_phy1: usb2-phy@120 {
118 compatible = "hisilicon,hi3798cv200-usb2-phy";
122 #address-cells = <1>;
123 #size-cells = <0>;
127 #phy-cells = <0>;
133 #phy-cells = <0>;
138 usb2_phy2: usb2-phy@124 {
139 compatible = "hisilicon,hi3798cv200-usb2-phy";
143 #address-cells = <1>;
144 #size-cells = <0>;
148 #phy-cells = <0>;
154 compatible = "hisilicon,hi3798cv200-combphy";
156 #phy-cells = <1>;
159 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
160 assigned-clock-rates = <100000000>;
161 hisilicon,fixed-mode = <PHY_TYPE_USB3>;
165 compatible = "hisilicon,hi3798cv200-combphy";
167 #phy-cells = <1>;
170 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
171 assigned-clock-rates = <100000000>;
172 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
177 compatible = "pinconf-single";
179 pinctrl-single,register-width = <32>;
180 pinctrl-single,function-mask = <7>;
181 pinctrl-single,gpio-range = <
182 &range 0 8 2 /* GPIO 0 */
183 &range 8 1 0 /* GPIO 1 */
184 &range 9 4 2
185 &range 13 1 0
186 &range 14 1 1
187 &range 15 1 0
188 &range 16 5 0 /* GPIO 2 */
189 &range 21 3 1
190 &range 24 4 1 /* GPIO 3 */
191 &range 28 2 2
192 &range 86 1 1
193 &range 87 1 0
194 &range 30 4 2 /* GPIO 4 */
195 &range 34 3 0
196 &range 37 1 2
197 &range 38 3 2 /* GPIO 6 */
198 &range 41 5 0
199 &range 46 8 1 /* GPIO 7 */
200 &range 54 8 1 /* GPIO 8 */
201 &range 64 7 1 /* GPIO 9 */
202 &range 71 1 0
203 &range 72 6 1 /* GPIO 10 */
204 &range 78 1 0
205 &range 79 1 1
206 &range 80 6 1 /* GPIO 11 */
207 &range 70 2 1
208 &range 88 8 0 /* GPIO 12 */
211 range: gpio-range { label
212 #pinctrl-single,gpio-range-cells = <3>;
221 clock-names = "apb_pclk";
230 clock-names = "apb_pclk";
235 compatible = "hisilicon,hix5hd2-i2c";
237 #address-cells = <1>;
238 #size-cells = <0>;
240 clock-frequency = <400000>;
246 compatible = "hisilicon,hix5hd2-i2c";
248 #address-cells = <1>;
249 #size-cells = <0>;
251 clock-frequency = <400000>;
257 compatible = "hisilicon,hix5hd2-i2c";
259 #address-cells = <1>;
260 #size-cells = <0>;
262 clock-frequency = <400000>;
268 compatible = "hisilicon,hix5hd2-i2c";
270 #address-cells = <1>;
271 #size-cells = <0>;
273 clock-frequency = <400000>;
279 compatible = "hisilicon,hix5hd2-i2c";
281 #address-cells = <1>;
282 #size-cells = <0>;
284 clock-frequency = <400000>;
293 num-cs = <1>;
294 cs-gpios = <&gpio7 1 0>;
296 clock-names = "apb_pclk";
297 #address-cells = <1>;
298 #size-cells = <0>;
303 compatible = "snps,dw-mshc";
308 clock-names = "ciu", "biu";
310 reset-names = "reset";
315 compatible = "hisilicon,hi3798cv200-dw-mshc";
322 clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
324 reset-names = "reset";
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 gpio-ranges = <&pmx0 0 0 8>;
338 clock-names = "apb_pclk";
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 gpio-ranges = <
358 clock-names = "apb_pclk";
366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
372 clock-names = "apb_pclk";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 gpio-ranges = <
391 clock-names = "apb_pclk";
399 gpio-controller;
400 #gpio-cells = <2>;
401 interrupt-controller;
402 #interrupt-cells = <2>;
403 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
405 clock-names = "apb_pclk";
413 gpio-controller;
414 #gpio-cells = <2>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
418 clock-names = "apb_pclk";
426 gpio-controller;
427 #gpio-cells = <2>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
430 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
432 clock-names = "apb_pclk";
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 gpio-ranges = <&pmx0 0 46 8>;
446 clock-names = "apb_pclk";
454 gpio-controller;
455 #gpio-cells = <2>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 gpio-ranges = <&pmx0 0 54 8>;
460 clock-names = "apb_pclk";
468 gpio-controller;
469 #gpio-cells = <2>;
470 interrupt-controller;
471 #interrupt-cells = <2>;
472 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
474 clock-names = "apb_pclk";
482 gpio-controller;
483 #gpio-cells = <2>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
488 clock-names = "apb_pclk";
496 gpio-controller;
497 #gpio-cells = <2>;
498 interrupt-controller;
499 #interrupt-cells = <2>;
500 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
502 clock-names = "apb_pclk";
510 gpio-controller;
511 #gpio-cells = <2>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 gpio-ranges = <&pmx0 0 88 8>;
516 clock-names = "apb_pclk";
521 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
527 clock-names = "mac_core", "mac_ifc";
531 reset-names = "mac_core", "mac_ifc", "phy";
536 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
542 clock-names = "mac_core", "mac_ifc";
546 reset-names = "mac_core", "mac_ifc", "phy";
551 compatible = "hisilicon,hix5hd2-ir";
559 compatible = "hisilicon,hi3798cv200-pcie";
563 reg-names = "control", "rc-dbi", "config";
564 #address-cells = <3>;
565 #size-cells = <2>;
567 bus-range = <0x00 0xff>;
568 num-lanes = <1>;
572 interrupt-names = "msi";
573 #interrupt-cells = <1>;
574 interrupt-map-mask = <0 0 0 0>;
575 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
580 clock-names = "aux", "pipe", "sys", "bus";
582 reset-names = "soft", "sys", "bus";
584 phy-names = "phy";
589 compatible = "generic-ohci";
595 clock-names = "bus", "clk12", "clk48";
597 reset-names = "bus";
599 phy-names = "usb";
604 compatible = "generic-ehci";
610 clock-names = "bus", "phy", "utmi";
614 reset-names = "bus", "phy", "utmi";
616 phy-names = "usb";