Lines Matching +full:imx7ulp +full:- +full:usdhc
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
51 #address-cells = <2>;
52 #size-cells = <0>;
54 /* We have 1 clusters with 4 Cortex-A35 cores */
57 compatible = "arm,cortex-a35";
59 enable-method = "psci";
60 next-level-cache = <&A35_L2>;
62 operating-points-v2 = <&a35_opp_table>;
63 #cooling-cells = <2>;
68 compatible = "arm,cortex-a35";
70 enable-method = "psci";
71 next-level-cache = <&A35_L2>;
73 operating-points-v2 = <&a35_opp_table>;
74 #cooling-cells = <2>;
79 compatible = "arm,cortex-a35";
81 enable-method = "psci";
82 next-level-cache = <&A35_L2>;
84 operating-points-v2 = <&a35_opp_table>;
85 #cooling-cells = <2>;
90 compatible = "arm,cortex-a35";
92 enable-method = "psci";
93 next-level-cache = <&A35_L2>;
95 operating-points-v2 = <&a35_opp_table>;
96 #cooling-cells = <2>;
99 A35_L2: l2-cache0 {
104 a35_opp_table: opp-table {
105 compatible = "operating-points-v2";
106 opp-shared;
108 opp-900000000 {
109 opp-hz = /bits/ 64 <900000000>;
110 opp-microvolt = <1000000>;
111 clock-latency-ns = <150000>;
114 opp-1200000000 {
115 opp-hz = /bits/ 64 <1200000000>;
116 opp-microvolt = <1100000>;
117 clock-latency-ns = <150000>;
118 opp-suspend;
122 gic: interrupt-controller@51a00000 {
123 compatible = "arm,gic-v3";
126 #interrupt-cells = <3>;
127 interrupt-controller;
131 reserved-memory {
132 #address-cells = <2>;
133 #size-cells = <2>;
138 no-map;
143 compatible = "arm,armv8-pmuv3";
148 compatible = "arm,psci-1.0";
153 compatible = "fsl,imx-scu";
154 mbox-names = "tx0",
161 clk: clock-controller {
162 compatible = "fsl,imx8qxp-clk";
163 #clock-cells = <1>;
165 clock-names = "xtal_32KHz", "xtal_24Mhz";
169 compatible = "fsl,imx8qxp-iomuxc";
172 ocotp: imx8qx-ocotp {
173 compatible = "fsl,imx8qxp-scu-ocotp";
174 #address-cells = <1>;
175 #size-cells = <1>;
178 pd: imx8qx-pd {
179 compatible = "fsl,imx8qxp-scu-pd";
180 #power-domain-cells = <1>;
183 scu_key: scu-key {
184 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
190 compatible = "fsl,imx8qxp-sc-rtc";
194 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
195 timeout-sec = <60>;
198 tsens: thermal-sensor {
199 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
200 #thermal-sensor-cells = <1>;
205 compatible = "arm,armv8-timer";
207 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
212 xtal32k: clock-xtal32k {
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <32768>;
216 clock-output-names = "xtal_32KHz";
219 xtal24m: clock-xtal24m {
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <24000000>;
223 clock-output-names = "xtal_24MHz";
227 compatible = "simple-bus";
228 #address-cells = <1>;
229 #size-cells = <1>;
232 adma_lpcg: clock-controller@59000000 {
233 compatible = "fsl,imx8qxp-lpcg-adma";
235 #clock-cells = <1>;
239 compatible = "fsl,imx8qxp-dsp";
244 clock-names = "ipg", "ocram", "core";
245 power-domains = <&pd IMX_SC_R_MU_13A>,
249 mbox-names = "txdb0", "txdb1",
255 memory-region = <&dsp_reserved>;
260 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
265 clock-names = "ipg", "baud";
266 power-domains = <&pd IMX_SC_R_UART_0>;
271 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
276 clock-names = "ipg", "baud";
277 power-domains = <&pd IMX_SC_R_UART_1>;
282 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
287 clock-names = "ipg", "baud";
288 power-domains = <&pd IMX_SC_R_UART_2>;
293 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
298 clock-names = "ipg", "baud";
299 power-domains = <&pd IMX_SC_R_UART_3>;
304 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
308 clock-names = "per";
309 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
310 assigned-clock-rates = <24000000>;
311 power-domains = <&pd IMX_SC_R_I2C_0>;
316 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
320 clock-names = "per";
321 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
322 assigned-clock-rates = <24000000>;
323 power-domains = <&pd IMX_SC_R_I2C_1>;
328 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
332 clock-names = "per";
333 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
334 assigned-clock-rates = <24000000>;
335 power-domains = <&pd IMX_SC_R_I2C_2>;
340 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
344 clock-names = "per";
345 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
346 assigned-clock-rates = <24000000>;
347 power-domains = <&pd IMX_SC_R_I2C_3>;
353 compatible = "simple-bus";
354 #address-cells = <1>;
355 #size-cells = <1>;
358 conn_lpcg: clock-controller@5b200000 {
359 compatible = "fsl,imx8qxp-lpcg-conn";
361 #clock-cells = <1>;
365 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
371 clock-names = "ipg", "per", "ahb";
372 power-domains = <&pd IMX_SC_R_SDHC_0>;
377 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
383 clock-names = "ipg", "per", "ahb";
384 power-domains = <&pd IMX_SC_R_SDHC_1>;
385 fsl,tuning-start-tap = <20>;
386 fsl,tuning-step= <2>;
391 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
397 clock-names = "ipg", "per", "ahb";
398 power-domains = <&pd IMX_SC_R_SDHC_2>;
403 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
413 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
414 fsl,num-tx-queues=<3>;
415 fsl,num-rx-queues=<3>;
416 power-domains = <&pd IMX_SC_R_ENET_0>;
421 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
431 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
432 fsl,num-tx-queues=<3>;
433 fsl,num-rx-queues=<3>;
434 power-domains = <&pd IMX_SC_R_ENET_1>;
440 compatible = "simple-bus";
441 #address-cells = <1>;
442 #size-cells = <1>;
445 ddr-pmu@5c020000 {
446 compatible = "fsl,imx8-ddr-pmu";
453 compatible = "simple-bus";
454 #address-cells = <1>;
455 #size-cells = <1>;
459 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
462 gpio-controller;
463 #gpio-cells = <2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 power-domains = <&pd IMX_SC_R_GPIO_0>;
470 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
473 gpio-controller;
474 #gpio-cells = <2>;
475 interrupt-controller;
476 #interrupt-cells = <2>;
477 power-domains = <&pd IMX_SC_R_GPIO_1>;
481 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
484 gpio-controller;
485 #gpio-cells = <2>;
486 interrupt-controller;
487 #interrupt-cells = <2>;
488 power-domains = <&pd IMX_SC_R_GPIO_2>;
492 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
495 gpio-controller;
496 #gpio-cells = <2>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 power-domains = <&pd IMX_SC_R_GPIO_3>;
503 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
506 gpio-controller;
507 #gpio-cells = <2>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 power-domains = <&pd IMX_SC_R_GPIO_4>;
514 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
517 gpio-controller;
518 #gpio-cells = <2>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
521 power-domains = <&pd IMX_SC_R_GPIO_5>;
525 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
528 gpio-controller;
529 #gpio-cells = <2>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
532 power-domains = <&pd IMX_SC_R_GPIO_6>;
536 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
539 gpio-controller;
540 #gpio-cells = <2>;
541 interrupt-controller;
542 #interrupt-cells = <2>;
543 power-domains = <&pd IMX_SC_R_GPIO_7>;
547 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
550 #mbox-cells = <2>;
555 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
558 #mbox-cells = <2>;
562 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
565 #mbox-cells = <2>;
570 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
573 #mbox-cells = <2>;
578 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
581 #mbox-cells = <2>;
586 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
589 #mbox-cells = <2>;
590 power-domains = <&pd IMX_SC_R_MU_13A>;
593 lsio_lpcg: clock-controller@5d400000 {
594 compatible = "fsl,imx8qxp-lpcg-lsio";
596 #clock-cells = <1>;
600 thermal_zones: thermal-zones {
601 cpu-thermal0 {
602 polling-delay-passive = <250>;
603 polling-delay = <2000>;
604 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
620 cooling-maps {
623 cooling-device =