Lines Matching +full:0 +full:x5c020000
52 #size-cells = <0>;
55 A35_0: cpu@0 {
58 reg = <0x0 0x0>;
69 reg = <0x0 0x1>;
80 reg = <0x0 0x2>;
91 reg = <0x0 0x3>;
124 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
125 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
137 reg = <0 0x92400000 0 0x2000000>;
157 mboxes = <&lsio_mu1 0 0
158 &lsio_mu1 1 0
214 #clock-cells = <0>;
221 #clock-cells = <0>;
230 ranges = <0x59000000 0x0 0x59000000 0x2000000>;
234 reg = <0x59000000 0x2000000>;
240 reg = <0x596e8000 0x88000>;
251 mboxes = <&lsio_mu13 2 0>,
253 <&lsio_mu13 3 0>,
261 reg = <0x5a060000 0x1000>;
272 reg = <0x5a070000 0x1000>;
283 reg = <0x5a080000 0x1000>;
294 reg = <0x5a090000 0x1000>;
305 reg = <0x5a800000 0x4000>;
317 reg = <0x5a810000 0x4000>;
329 reg = <0x5a820000 0x4000>;
341 reg = <0x5a830000 0x4000>;
356 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
360 reg = <0x5b200000 0xb0000>;
367 reg = <0x5b010000 0x10000>;
379 reg = <0x5b020000 0x10000>;
393 reg = <0x5b030000 0x10000>;
404 reg = <0x5b040000 0x10000>;
422 reg = <0x5b050000 0x10000>;
443 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
447 reg = <0x5c020000 0x10000>;
456 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
460 reg = <0x5d080000 0x10000>;
471 reg = <0x5d090000 0x10000>;
482 reg = <0x5d0a0000 0x10000>;
493 reg = <0x5d0b0000 0x10000>;
504 reg = <0x5d0c0000 0x10000>;
515 reg = <0x5d0d0000 0x10000>;
526 reg = <0x5d0e0000 0x10000>;
537 reg = <0x5d0f0000 0x10000>;
548 reg = <0x5d1b0000 0x10000>;
556 reg = <0x5d1c0000 0x10000>;
563 reg = <0x5d1d0000 0x10000>;
571 reg = <0x5d1e0000 0x10000>;
579 reg = <0x5d1f0000 0x10000>;
587 reg = <0x5d280000 0x10000>;
595 reg = <0x5d400000 0x400000>;