Lines Matching +full:imx6q +full:- +full:gpc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mq-pinfunc.h"
17 interrupt-parent = <&gpc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
44 ckil: clock-ckil {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <32768>;
48 clock-output-names = "ckil";
51 osc_25m: clock-osc-25m {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <25000000>;
55 clock-output-names = "osc_25m";
58 osc_27m: clock-osc-27m {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <27000000>;
62 clock-output-names = "osc_27m";
65 clk_ext1: clock-ext1 {
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <133000000>;
69 clock-output-names = "clk_ext1";
72 clk_ext2: clock-ext2 {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <133000000>;
76 clock-output-names = "clk_ext2";
79 clk_ext3: clock-ext3 {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <133000000>;
83 clock-output-names = "clk_ext3";
86 clk_ext4: clock-ext4 {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency= <133000000>;
90 clock-output-names = "clk_ext4";
94 #address-cells = <1>;
95 #size-cells = <0>;
99 compatible = "arm,cortex-a53";
101 clock-latency = <61036>; /* two CLK32 periods */
103 enable-method = "psci";
104 next-level-cache = <&A53_L2>;
105 operating-points-v2 = <&a53_opp_table>;
106 #cooling-cells = <2>;
107 nvmem-cells = <&cpu_speed_grade>;
108 nvmem-cell-names = "speed_grade";
113 compatible = "arm,cortex-a53";
115 clock-latency = <61036>; /* two CLK32 periods */
117 enable-method = "psci";
118 next-level-cache = <&A53_L2>;
119 operating-points-v2 = <&a53_opp_table>;
120 #cooling-cells = <2>;
125 compatible = "arm,cortex-a53";
127 clock-latency = <61036>; /* two CLK32 periods */
129 enable-method = "psci";
130 next-level-cache = <&A53_L2>;
131 operating-points-v2 = <&a53_opp_table>;
132 #cooling-cells = <2>;
137 compatible = "arm,cortex-a53";
139 clock-latency = <61036>; /* two CLK32 periods */
141 enable-method = "psci";
142 next-level-cache = <&A53_L2>;
143 operating-points-v2 = <&a53_opp_table>;
144 #cooling-cells = <2>;
147 A53_L2: l2-cache0 {
152 a53_opp_table: opp-table {
153 compatible = "operating-points-v2";
154 opp-shared;
156 opp-800000000 {
157 opp-hz = /bits/ 64 <800000000>;
158 opp-microvolt = <900000>;
160 opp-supported-hw = <0xf>, <0x4>;
161 clock-latency-ns = <150000>;
162 opp-suspend;
165 opp-1000000000 {
166 opp-hz = /bits/ 64 <1000000000>;
167 opp-microvolt = <900000>;
169 opp-supported-hw = <0xe>, <0x3>;
170 clock-latency-ns = <150000>;
171 opp-suspend;
174 opp-1300000000 {
175 opp-hz = /bits/ 64 <1300000000>;
176 opp-microvolt = <1000000>;
177 opp-supported-hw = <0xc>, <0x4>;
178 clock-latency-ns = <150000>;
179 opp-suspend;
182 opp-1500000000 {
183 opp-hz = /bits/ 64 <1500000000>;
184 opp-microvolt = <1000000>;
185 opp-supported-hw = <0x8>, <0x3>;
186 clock-latency-ns = <150000>;
187 opp-suspend;
192 compatible = "arm,cortex-a53-pmu";
194 interrupt-parent = <&gic>;
195 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
199 compatible = "arm,psci-1.0";
203 thermal-zones {
204 cpu_thermal: cpu-thermal {
205 polling-delay-passive = <250>;
206 polling-delay = <2000>;
207 thermal-sensors = <&tmu 0>;
210 cpu_alert: cpu-alert {
216 cpu-crit {
223 cooling-maps {
226 cooling-device =
235 gpu-thermal {
236 polling-delay-passive = <250>;
237 polling-delay = <2000>;
238 thermal-sensors = <&tmu 1>;
241 gpu_alert: gpu-alert {
247 gpu-crit {
254 cooling-maps {
257 cooling-device =
263 vpu-thermal {
264 polling-delay-passive = <250>;
265 polling-delay = <2000>;
266 thermal-sensors = <&tmu 2>;
269 vpu-crit {
279 compatible = "arm,armv8-timer";
281 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
284 interrupt-parent = <&gic>;
285 arm,no-tick-in-suspend;
289 compatible = "simple-bus";
290 #address-cells = <1>;
291 #size-cells = <1>;
293 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
296 compatible = "fsl,aips-bus", "simple-bus";
298 #address-cells = <1>;
299 #size-cells = <1>;
303 #sound-dai-cells = <0>;
304 compatible = "fsl,imx8mq-sai";
310 clock-names = "bus", "mclk1", "mclk2", "mclk3";
312 dma-names = "rx", "tx";
317 #sound-dai-cells = <0>;
318 compatible = "fsl,imx8mq-sai";
324 clock-names = "bus", "mclk1", "mclk2", "mclk3";
326 dma-names = "rx", "tx";
331 #sound-dai-cells = <0>;
332 compatible = "fsl,imx8mq-sai";
338 clock-names = "bus", "mclk1", "mclk2", "mclk3";
340 dma-names = "rx", "tx";
345 #sound-dai-cells = <0>;
346 compatible = "fsl,imx8mq-sai";
352 clock-names = "bus", "mclk1", "mclk2", "mclk3";
354 dma-names = "rx", "tx";
359 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 gpio-ranges = <&iomuxc 0 10 30>;
372 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
377 gpio-controller;
378 #gpio-cells = <2>;
379 interrupt-controller;
380 #interrupt-cells = <2>;
381 gpio-ranges = <&iomuxc 0 40 21>;
385 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 gpio-ranges = <&iomuxc 0 61 26>;
398 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
403 gpio-controller;
404 #gpio-cells = <2>;
405 interrupt-controller;
406 #interrupt-cells = <2>;
407 gpio-ranges = <&iomuxc 0 87 32>;
411 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 gpio-ranges = <&iomuxc 0 119 30>;
424 compatible = "fsl,imx8mq-tmu";
428 little-endian;
429 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
430 fsl,tmu-calibration = <0x00000000 0x00000023
473 #thermal-sensor-cells = <1>;
477 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
485 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
493 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
501 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
506 clock-names = "ipg", "ahb";
507 #dma-cells = <3>;
508 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
511 lcdif: lcd-controller@30320000 {
512 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
516 clock-names = "pix";
517 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
521 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
524 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
529 remote-endpoint = <&mipi_dsi_lcdif_in>;
535 compatible = "fsl,imx8mq-iomuxc";
540 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
541 "syscon", "simple-mfd";
544 mux: mux-controller {
545 compatible = "mmio-mux";
546 #mux-control-cells = <1>;
547 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
552 compatible = "fsl,imx8mq-ocotp", "syscon";
555 #address-cells = <1>;
556 #size-cells = <1>;
558 cpu_speed_grade: speed-grade@10 {
564 compatible = "fsl,imx8mq-anatop", "syscon";
570 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
573 snvs_rtc: snvs-rtc-lp{
574 compatible = "fsl,sec-v4.0-mon-rtc-lp";
580 clock-names = "snvs-rtc";
583 snvs_pwrkey: snvs-powerkey {
584 compatible = "fsl,sec-v4.0-pwrkey";
588 clock-names = "snvs-pwrkey";
590 wakeup-source;
595 clk: clock-controller@30380000 {
596 compatible = "fsl,imx8mq-ccm";
600 #clock-cells = <1>;
604 clock-names = "ckil", "osc_25m", "osc_27m",
607 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
610 assigned-clock-rates = <0>, <0>,
612 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
616 src: reset-controller@30390000 {
617 compatible = "fsl,imx8mq-src", "syscon";
620 #reset-cells = <1>;
623 gpc: gpc@303a0000 { label
624 compatible = "fsl,imx8mq-gpc";
627 interrupt-parent = <&gic>;
628 interrupt-controller;
629 #interrupt-cells = <3>;
632 #address-cells = <1>;
633 #size-cells = <0>;
635 pgc_mipi: power-domain@0 {
636 #power-domain-cells = <0>;
655 pgc_pcie: power-domain@1 {
656 #power-domain-cells = <0>;
658 power-domains = <&pgc_pcie2>;
661 pgc_otg1: power-domain@2 {
662 #power-domain-cells = <0>;
666 pgc_otg2: power-domain@3 {
667 #power-domain-cells = <0>;
671 pgc_ddr1: power-domain@4 {
672 #power-domain-cells = <0>;
676 pgc_gpu: power-domain@5 {
677 #power-domain-cells = <0>;
685 pgc_vpu: power-domain@6 {
686 #power-domain-cells = <0>;
691 pgc_disp: power-domain@7 {
692 #power-domain-cells = <0>;
696 pgc_mipi_csi1: power-domain@8 {
697 #power-domain-cells = <0>;
701 pgc_mipi_csi2: power-domain@9 {
702 #power-domain-cells = <0>;
706 pgc_pcie2: power-domain@a {
707 #power-domain-cells = <0>;
715 compatible = "fsl,aips-bus", "simple-bus";
717 #address-cells = <1>;
718 #size-cells = <1>;
722 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
727 clock-names = "ipg", "per";
728 #pwm-cells = <2>;
733 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
738 clock-names = "ipg", "per";
739 #pwm-cells = <2>;
744 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
749 clock-names = "ipg", "per";
750 #pwm-cells = <2>;
755 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
760 clock-names = "ipg", "per";
761 #pwm-cells = <2>;
766 compatible = "nxp,sysctr-timer";
770 clock-names = "per";
775 compatible = "fsl,aips-bus", "simple-bus";
777 #address-cells = <1>;
778 #size-cells = <1>;
783 #address-cells = <1>;
784 #size-cells = <0>;
785 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
790 clock-names = "ipg", "per";
795 #address-cells = <1>;
796 #size-cells = <0>;
797 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
802 clock-names = "ipg", "per";
807 #address-cells = <1>;
808 #size-cells = <0>;
809 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
814 clock-names = "ipg", "per";
819 compatible = "fsl,imx8mq-uart",
820 "fsl,imx6q-uart";
825 clock-names = "ipg", "per";
830 compatible = "fsl,imx8mq-uart",
831 "fsl,imx6q-uart";
836 clock-names = "ipg", "per";
841 compatible = "fsl,imx8mq-uart",
842 "fsl,imx6q-uart";
847 clock-names = "ipg", "per";
852 #sound-dai-cells = <0>;
853 compatible = "fsl,imx8mq-sai";
859 clock-names = "bus", "mclk1", "mclk2", "mclk3";
861 dma-names = "rx", "tx";
866 #sound-dai-cells = <0>;
867 compatible = "fsl,imx8mq-sai";
873 clock-names = "bus", "mclk1", "mclk2", "mclk3";
875 dma-names = "rx", "tx";
880 compatible = "fsl,sec-v4.0";
881 #address-cells = <1>;
882 #size-cells = <1>;
888 clock-names = "aclk", "ipg";
891 compatible = "fsl,sec-v4.0-job-ring";
897 compatible = "fsl,sec-v4.0-job-ring";
903 compatible = "fsl,sec-v4.0-job-ring";
909 mipi_dsi: mipi-dsi@30a00000 {
910 compatible = "fsl,imx8mq-nwl-dsi";
917 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
918 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
921 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
923 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
925 mux-controls = <&mux 0>;
926 power-domains = <&pgc_mipi>;
928 phy-names = "dphy";
933 reset-names = "byte", "dpi", "esc", "pclk";
937 #address-cells = <1>;
938 #size-cells = <0>;
942 #address-cells = <1>;
943 #size-cells = <0>;
946 remote-endpoint = <&lcdif_mipi_dsi>;
953 compatible = "fsl,imx8mq-mipi-dphy";
956 clock-names = "phy_ref";
957 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
958 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
959 assigned-clock-rates = <24000000>;
960 #phy-cells = <0>;
961 power-domains = <&pgc_mipi>;
966 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
970 #address-cells = <1>;
971 #size-cells = <0>;
976 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
980 #address-cells = <1>;
981 #size-cells = <0>;
986 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
990 #address-cells = <1>;
991 #size-cells = <0>;
996 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1006 compatible = "fsl,imx8mq-uart",
1007 "fsl,imx6q-uart";
1012 clock-names = "ipg", "per";
1017 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1021 #mbox-cells = <2>;
1025 compatible = "fsl,imx8mq-usdhc",
1026 "fsl,imx7d-usdhc";
1032 clock-names = "ipg", "ahb", "per";
1033 fsl,tuning-start-tap = <20>;
1034 fsl,tuning-step = <2>;
1035 bus-width = <4>;
1040 compatible = "fsl,imx8mq-usdhc",
1041 "fsl,imx7d-usdhc";
1047 clock-names = "ipg", "ahb", "per";
1048 fsl,tuning-start-tap = <20>;
1049 fsl,tuning-step = <2>;
1050 bus-width = <4>;
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1060 reg-names = "QuadSPI", "QuadSPI-memory";
1064 clock-names = "qspi_en", "qspi";
1069 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1074 clock-names = "ipg", "ahb";
1075 #dma-cells = <3>;
1076 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1080 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1091 clock-names = "ipg", "ahb", "ptp",
1093 fsl,num-tx-queues = <3>;
1094 fsl,num-rx-queues = <3>;
1100 compatible = "fsl,aips-bus", "simple-bus";
1102 #address-cells = <1>;
1103 #size-cells = <1>;
1106 irqsteer: interrupt-controller@32e2d000 {
1107 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1111 clock-names = "ipg";
1113 fsl,num-irqs = <64>;
1114 interrupt-controller;
1115 #interrupt-cells = <1>;
1127 clock-names = "core", "shader", "bus", "reg";
1128 #cooling-cells = <2>;
1129 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1134 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1139 assigned-clock-rates = <800000000>, <800000000>,
1141 power-domains = <&pgc_gpu>;
1145 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1150 clock-names = "bus_early", "ref", "suspend";
1151 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1153 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1155 assigned-clock-rates = <500000000>, <100000000>;
1158 phy-names = "usb2-phy", "usb3-phy";
1159 power-domains = <&pgc_otg1>;
1160 usb3-resume-missing-cas;
1164 usb3_phy0: usb-phy@381f0040 {
1165 compatible = "fsl,imx8mq-usb-phy";
1168 clock-names = "phy";
1169 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1170 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1171 assigned-clock-rates = <100000000>;
1172 #phy-cells = <0>;
1177 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1182 clock-names = "bus_early", "ref", "suspend";
1183 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1185 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1187 assigned-clock-rates = <500000000>, <100000000>;
1190 phy-names = "usb2-phy", "usb3-phy";
1191 power-domains = <&pgc_otg2>;
1192 usb3-resume-missing-cas;
1196 usb3_phy1: usb-phy@382f0040 {
1197 compatible = "fsl,imx8mq-usb-phy";
1200 clock-names = "phy";
1201 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1202 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1203 assigned-clock-rates = <100000000>;
1204 #phy-cells = <0>;
1208 vpu: video-codec@38300000 {
1209 compatible = "nxp,imx8mq-vpu";
1213 reg-names = "g1", "g2", "ctrl";
1216 interrupt-names = "g1", "g2";
1220 clock-names = "g1", "g2", "bus";
1221 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
1225 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
1229 assigned-clock-rates = <600000000>, <600000000>,
1231 power-domains = <&pgc_vpu>;
1235 compatible = "fsl,imx8mq-pcie";
1238 reg-names = "dbi", "config";
1239 #address-cells = <3>;
1240 #size-cells = <2>;
1242 bus-range = <0x00 0xff>;
1244 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1245 num-lanes = <1>;
1246 num-viewport = <4>;
1248 interrupt-names = "msi";
1249 #interrupt-cells = <1>;
1250 interrupt-map-mask = <0 0 0 0x7>;
1251 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1255 fsl,max-link-speed = <2>;
1256 power-domains = <&pgc_pcie>;
1260 reset-names = "pciephy", "apps", "turnoff";
1265 compatible = "fsl,imx8mq-pcie";
1268 reg-names = "dbi", "config";
1269 #address-cells = <3>;
1270 #size-cells = <2>;
1273 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1274 num-lanes = <1>;
1275 num-viewport = <4>;
1277 interrupt-names = "msi";
1278 #interrupt-cells = <1>;
1279 interrupt-map-mask = <0 0 0 0x7>;
1280 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1284 fsl,max-link-speed = <2>;
1285 power-domains = <&pgc_pcie>;
1289 reset-names = "pciephy", "apps", "turnoff";
1293 gic: interrupt-controller@38800000 {
1294 compatible = "arm,gic-v3";
1300 #interrupt-cells = <3>;
1301 interrupt-controller;
1303 interrupt-parent = <&gic>;
1306 ddrc: memory-controller@3d400000 {
1307 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1309 clock-names = "core", "pll", "alt", "apb";
1316 ddr-pmu@3d800000 {
1317 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1319 interrupt-parent = <&gic>;