Lines Matching +full:0 +full:x30380000
46 #clock-cells = <0>;
53 #clock-cells = <0>;
60 #clock-cells = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
88 #clock-cells = <0>;
95 #size-cells = <0>;
97 A53_0: cpu@0 {
100 reg = <0x0>;
114 reg = <0x1>;
126 reg = <0x2>;
138 reg = <0x3>;
160 opp-supported-hw = <0xf>, <0x4>;
169 opp-supported-hw = <0xe>, <0x3>;
177 opp-supported-hw = <0xc>, <0x4>;
185 opp-supported-hw = <0x8>, <0x3>;
207 thermal-sensors = <&tmu 0>;
288 soc@0 {
292 ranges = <0x0 0x0 0x0 0x3e000000>;
293 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
297 reg = <0x30000000 0x400000>;
300 ranges = <0x30000000 0x30000000 0x400000>;
303 #sound-dai-cells = <0>;
305 reg = <0x30010000 0x10000>;
311 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
317 #sound-dai-cells = <0>;
319 reg = <0x30030000 0x10000>;
325 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
331 #sound-dai-cells = <0>;
333 reg = <0x30040000 0x10000>;
339 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
345 #sound-dai-cells = <0>;
347 reg = <0x30050000 0x10000>;
353 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
360 reg = <0x30200000 0x10000>;
368 gpio-ranges = <&iomuxc 0 10 30>;
373 reg = <0x30210000 0x10000>;
381 gpio-ranges = <&iomuxc 0 40 21>;
386 reg = <0x30220000 0x10000>;
394 gpio-ranges = <&iomuxc 0 61 26>;
399 reg = <0x30230000 0x10000>;
407 gpio-ranges = <&iomuxc 0 87 32>;
412 reg = <0x30240000 0x10000>;
420 gpio-ranges = <&iomuxc 0 119 30>;
425 reg = <0x30260000 0x10000>;
429 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
430 fsl,tmu-calibration = <0x00000000 0x00000023
431 0x00000001 0x00000029
432 0x00000002 0x0000002f
433 0x00000003 0x00000035
434 0x00000004 0x0000003d
435 0x00000005 0x00000043
436 0x00000006 0x0000004b
437 0x00000007 0x00000051
438 0x00000008 0x00000057
439 0x00000009 0x0000005f
440 0x0000000a 0x00000067
441 0x0000000b 0x0000006f
443 0x00010000 0x0000001b
444 0x00010001 0x00000023
445 0x00010002 0x0000002b
446 0x00010003 0x00000033
447 0x00010004 0x0000003b
448 0x00010005 0x00000043
449 0x00010006 0x0000004b
450 0x00010007 0x00000055
451 0x00010008 0x0000005d
452 0x00010009 0x00000067
453 0x0001000a 0x00000070
455 0x00020000 0x00000017
456 0x00020001 0x00000023
457 0x00020002 0x0000002d
458 0x00020003 0x00000037
459 0x00020004 0x00000041
460 0x00020005 0x0000004b
461 0x00020006 0x00000057
462 0x00020007 0x00000063
463 0x00020008 0x0000006f
465 0x00030000 0x00000015
466 0x00030001 0x00000021
467 0x00030002 0x0000002d
468 0x00030003 0x00000039
469 0x00030004 0x00000045
470 0x00030005 0x00000053
471 0x00030006 0x0000005f
472 0x00030007 0x00000071>;
478 reg = <0x30280000 0x10000>;
486 reg = <0x30290000 0x10000>;
494 reg = <0x302a0000 0x10000>;
502 reg = <0x302c0000 0x10000>;
513 reg = <0x30320000 0x10000>;
524 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
527 port@0 {
536 reg = <0x30330000 0x10000>;
542 reg = <0x30340000 0x10000>;
547 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
553 reg = <0x30350000 0x10000>;
559 reg = <0x10 4>;
565 reg = <0x30360000 0x10000>;
570 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
571 reg = <0x30370000 0x10000>;
574 compatible = "fsl,sec-v4.0-mon-rtc-lp";
576 offset = <0x34>;
584 compatible = "fsl,sec-v4.0-pwrkey";
597 reg = <0x30380000 0x10000>;
610 assigned-clock-rates = <0>, <0>,
618 reg = <0x30390000 0x10000>;
625 reg = <0x303a0000 0x10000>;
633 #size-cells = <0>;
635 pgc_mipi: power-domain@0 {
636 #power-domain-cells = <0>;
656 #power-domain-cells = <0>;
662 #power-domain-cells = <0>;
667 #power-domain-cells = <0>;
672 #power-domain-cells = <0>;
677 #power-domain-cells = <0>;
686 #power-domain-cells = <0>;
692 #power-domain-cells = <0>;
697 #power-domain-cells = <0>;
702 #power-domain-cells = <0>;
707 #power-domain-cells = <0>;
716 reg = <0x30400000 0x400000>;
719 ranges = <0x30400000 0x30400000 0x400000>;
723 reg = <0x30660000 0x10000>;
734 reg = <0x30670000 0x10000>;
745 reg = <0x30680000 0x10000>;
756 reg = <0x30690000 0x10000>;
767 reg = <0x306a0000 0x20000>;
776 reg = <0x30800000 0x400000>;
779 ranges = <0x30800000 0x30800000 0x400000>,
780 <0x08000000 0x08000000 0x10000000>;
784 #size-cells = <0>;
786 reg = <0x30820000 0x10000>;
796 #size-cells = <0>;
798 reg = <0x30830000 0x10000>;
808 #size-cells = <0>;
810 reg = <0x30840000 0x10000>;
821 reg = <0x30860000 0x10000>;
832 reg = <0x30880000 0x10000>;
843 reg = <0x30890000 0x10000>;
852 #sound-dai-cells = <0>;
854 reg = <0x308b0000 0x10000>;
860 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
866 #sound-dai-cells = <0>;
868 reg = <0x308c0000 0x10000>;
874 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
880 compatible = "fsl,sec-v4.0";
883 reg = <0x30900000 0x40000>;
884 ranges = <0 0x30900000 0x40000>;
891 compatible = "fsl,sec-v4.0-job-ring";
892 reg = <0x1000 0x1000>;
897 compatible = "fsl,sec-v4.0-job-ring";
898 reg = <0x2000 0x1000>;
903 compatible = "fsl,sec-v4.0-job-ring";
904 reg = <0x3000 0x1000>;
911 reg = <0x30a00000 0x300>;
925 mux-controls = <&mux 0>;
938 #size-cells = <0>;
940 port@0 {
941 reg = <0>;
943 #size-cells = <0>;
944 mipi_dsi_lcdif_in: endpoint@0 {
945 reg = <0>;
954 reg = <0x30a00300 0x100>;
960 #phy-cells = <0>;
967 reg = <0x30a20000 0x10000>;
971 #size-cells = <0>;
977 reg = <0x30a30000 0x10000>;
981 #size-cells = <0>;
987 reg = <0x30a40000 0x10000>;
991 #size-cells = <0>;
997 reg = <0x30a50000 0x10000>;
1001 #size-cells = <0>;
1008 reg = <0x30a60000 0x10000>;
1018 reg = <0x30aa0000 0x10000>;
1027 reg = <0x30b40000 0x10000>;
1042 reg = <0x30b50000 0x10000>;
1056 #size-cells = <0>;
1058 reg = <0x30bb0000 0x10000>,
1059 <0x08000000 0x10000000>;
1070 reg = <0x30bd0000 0x10000>;
1081 reg = <0x30be0000 0x10000>;
1101 reg = <0x32c00000 0x400000>;
1104 ranges = <0x32c00000 0x32c00000 0x400000>;
1108 reg = <0x32e2d000 0x1000>;
1112 fsl,channel = <0>;
1121 reg = <0x38000000 0x40000>;
1140 <800000000>, <800000000>, <0>;
1146 reg = <0x38100000 0x10000>;
1166 reg = <0x381f0040 0x40>;
1172 #phy-cells = <0>;
1178 reg = <0x38200000 0x10000>;
1198 reg = <0x382f0040 0x40>;
1204 #phy-cells = <0>;
1210 reg = <0x38300000 0x10000>,
1211 <0x38310000 0x10000>,
1212 <0x38320000 0x10000>;
1230 <800000000>, <0>;
1236 reg = <0x33800000 0x400000>,
1237 <0x1ff00000 0x80000>;
1242 bus-range = <0x00 0xff>;
1243 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1244 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1250 interrupt-map-mask = <0 0 0 0x7>;
1251 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1252 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1253 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1254 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1266 reg = <0x33c00000 0x400000>,
1267 <0x27f00000 0x80000>;
1272 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1273 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1279 interrupt-map-mask = <0 0 0 0x7>;
1280 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1281 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1282 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1283 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1295 reg = <0x38800000 0x10000>, /* GIC Dist */
1296 <0x38880000 0xc0000>, /* GICR */
1297 <0x31000000 0x2000>, /* GICC */
1298 <0x31010000 0x2000>, /* GICV */
1299 <0x31020000 0x2000>; /* GICH */
1308 reg = <0x3d400000 0x400000>;
1318 reg = <0x3d800000 0x400000>;