Lines Matching +full:0 +full:x19
21 reg = <0x00000000 0x40000000 0 0x80000000>;
27 pinctrl-0 = <&pinctrl_gpio_keys>;
37 reg_vref_0v9: regulator-vref-0v9 {
39 regulator-name = "vref-0v9";
76 pinctrl-0 = <&pinctrl_fec1>;
84 #size-cells = <0>;
97 pinctrl-0 = <&pinctrl_i2c1>;
103 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
104 reg = <0x70>;
107 #size-cells = <0>;
109 i2c1a: i2c1@0 {
110 reg = <0>;
112 #size-cells = <0>;
117 pinctrl-0 = <&pinctrl_reg_arm_dram>;
118 reg = <0x60>;
129 #size-cells = <0>;
134 pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
135 reg = <0x60>;
146 #size-cells = <0>;
151 pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
152 reg = <0x60>;
163 #size-cells = <0>;
168 pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
169 reg = <0x68>;
179 pinctrl-0 = <&pinctrl_uart1>;
187 pinctrl-0 = <&pinctrl_uart2>;
198 pinctrl-0 = <&pinctrl_usdhc1>;
206 pinctrl-0 = <&pinctrl_wdog>;
213 pinctrl-0 = <&pinctrl_hog>;
218 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
219 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
220 MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
221 MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
222 MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
223 MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
224 MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
225 MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
226 MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
227 MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
228 MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
229 MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
230 MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
231 MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
232 MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
233 MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
236 MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
237 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
238 MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
239 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
240 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
243 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
244 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
245 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
246 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
247 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
248 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
251 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
252 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
253 MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
254 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
255 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
256 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
257 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
260 MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
262 MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
264 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
266 MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
268 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
271 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
273 MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
279 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
280 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
281 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
282 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
283 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
284 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
285 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
286 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
287 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
288 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
289 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
290 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
291 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
292 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
293 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
294 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
300 MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
307 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
308 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
314 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
320 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
326 MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
332 MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
338 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
344 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
345 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
351 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
352 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
358 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
359 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
360 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
361 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
362 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
363 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
364 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
365 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
366 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
367 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
368 MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
374 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
375 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
376 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
377 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
378 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
379 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
380 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
381 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
382 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
383 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
389 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
390 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
391 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
392 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
393 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
394 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
395 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
396 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
397 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
398 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
404 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6