Lines Matching +full:imx51 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a53";
49 clock-latency = <61036>;
51 enable-method = "psci";
52 next-level-cache = <&A53_L2>;
53 #cooling-cells = <2>;
58 compatible = "arm,cortex-a53";
60 clock-latency = <61036>;
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
64 #cooling-cells = <2>;
69 compatible = "arm,cortex-a53";
71 clock-latency = <61036>;
73 enable-method = "psci";
74 next-level-cache = <&A53_L2>;
75 #cooling-cells = <2>;
80 compatible = "arm,cortex-a53";
82 clock-latency = <61036>;
84 enable-method = "psci";
85 next-level-cache = <&A53_L2>;
86 #cooling-cells = <2>;
89 A53_L2: l2-cache0 {
94 osc_32k: clock-osc-32k {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <32768>;
98 clock-output-names = "osc_32k";
101 osc_24m: clock-osc-24m {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <24000000>;
105 clock-output-names = "osc_24m";
108 clk_ext1: clock-ext1 {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <133000000>;
112 clock-output-names = "clk_ext1";
115 clk_ext2: clock-ext2 {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <133000000>;
119 clock-output-names = "clk_ext2";
122 clk_ext3: clock-ext3 {
123 compatible = "fixed-clock";
124 #clock-cells = <0>;
125 clock-frequency = <133000000>;
126 clock-output-names = "clk_ext3";
129 clk_ext4: clock-ext4 {
130 compatible = "fixed-clock";
131 #clock-cells = <0>;
132 clock-frequency= <133000000>;
133 clock-output-names = "clk_ext4";
137 compatible = "arm,psci-1.0";
141 thermal-zones {
142 cpu-thermal {
143 polling-delay-passive = <250>;
144 polling-delay = <2000>;
145 thermal-sensors = <&tmu 0>;
160 cooling-maps {
163 cooling-device =
172 soc-thermal {
173 polling-delay-passive = <250>;
174 polling-delay = <2000>;
175 thermal-sensors = <&tmu 1>;
190 cooling-maps {
193 cooling-device =
204 compatible = "arm,armv8-timer";
209 clock-frequency = <8000000>;
210 arm,no-tick-in-suspend;
214 compatible = "simple-bus";
215 #address-cells = <1>;
216 #size-cells = <1>;
220 compatible = "fsl,aips-bus", "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
227 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
232 gpio-controller;
233 #gpio-cells = <2>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 gpio-ranges = <&iomuxc 0 5 30>;
240 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 gpio-ranges = <&iomuxc 0 35 21>;
253 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
266 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
271 gpio-controller;
272 #gpio-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 gpio-ranges = <&iomuxc 0 82 32>;
279 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 gpio-ranges = <&iomuxc 0 114 30>;
292 compatible = "fsl,imx8mp-tmu";
295 #thermal-sensor-cells = <1>;
299 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
307 compatible = "fsl,imx8mp-iomuxc";
311 gpr: iomuxc-gpr@30340000 {
312 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
317 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
321 #address-cells = <1>;
322 #size-cells = <1>;
324 cpu_speed_grade: speed-grade@10 {
330 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
336 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
339 snvs_rtc: snvs-rtc-lp {
340 compatible = "fsl,sec-v4.0-mon-rtc-lp";
346 clock-names = "snvs-rtc";
349 snvs_pwrkey: snvs-powerkey {
350 compatible = "fsl,sec-v4.0-pwrkey";
354 clock-names = "snvs-pwrkey";
356 wakeup-source;
361 clk: clock-controller@30380000 {
362 compatible = "fsl,imx8mp-ccm";
364 #clock-cells = <1>;
367 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
369 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
379 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
386 assigned-clock-rates = <0>, <0>,
397 src: reset-controller@30390000 {
398 compatible = "fsl,imx8mp-src", "syscon";
401 #reset-cells = <1>;
406 compatible = "fsl,aips-bus", "simple-bus";
408 #address-cells = <1>;
409 #size-cells = <1>;
413 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
418 clock-names = "ipg", "per";
419 #pwm-cells = <2>;
424 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
429 clock-names = "ipg", "per";
430 #pwm-cells = <2>;
435 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
440 clock-names = "ipg", "per";
441 #pwm-cells = <2>;
446 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
451 clock-names = "ipg", "per";
452 #pwm-cells = <2>;
457 compatible = "nxp,sysctr-timer";
461 clock-names = "per";
466 compatible = "fsl,aips-bus", "simple-bus";
468 #address-cells = <1>;
469 #size-cells = <1>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
480 clock-names = "ipg", "per";
482 dma-names = "rx", "tx";
487 #address-cells = <1>;
488 #size-cells = <0>;
489 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
494 clock-names = "ipg", "per";
496 dma-names = "rx", "tx";
501 #address-cells = <1>;
502 #size-cells = <0>;
503 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
508 clock-names = "ipg", "per";
510 dma-names = "rx", "tx";
515 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
520 clock-names = "ipg", "per";
522 dma-names = "rx", "tx";
527 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
532 clock-names = "ipg", "per";
534 dma-names = "rx", "tx";
539 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
544 clock-names = "ipg", "per";
549 compatible = "fsl,sec-v4.0";
550 #address-cells = <1>;
551 #size-cells = <1>;
557 clock-names = "aclk", "ipg";
560 compatible = "fsl,sec-v4.0-job-ring";
566 compatible = "fsl,sec-v4.0-job-ring";
572 compatible = "fsl,sec-v4.0-job-ring";
578 i2c1: i2c@30a20000 {
579 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
580 #address-cells = <1>;
581 #size-cells = <0>;
588 i2c2: i2c@30a30000 {
589 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
590 #address-cells = <1>;
591 #size-cells = <0>;
598 i2c3: i2c@30a40000 {
599 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
600 #address-cells = <1>;
601 #size-cells = <0>;
608 i2c4: i2c@30a50000 {
609 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
610 #address-cells = <1>;
611 #size-cells = <0>;
619 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
624 clock-names = "ipg", "per";
626 dma-names = "rx", "tx";
631 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
635 #mbox-cells = <2>;
638 i2c5: i2c@30ad0000 {
639 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
640 #address-cells = <1>;
641 #size-cells = <0>;
648 i2c6: i2c@30ae0000 {
649 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
650 #address-cells = <1>;
651 #size-cells = <0>;
659 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
665 clock-names = "ipg", "ahb", "per";
666 fsl,tuning-start-tap = <20>;
667 fsl,tuning-step= <2>;
668 bus-width = <4>;
673 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
679 clock-names = "ipg", "ahb", "per";
680 fsl,tuning-start-tap = <20>;
681 fsl,tuning-step= <2>;
682 bus-width = <4>;
687 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
693 clock-names = "ipg", "ahb", "per";
694 fsl,tuning-start-tap = <20>;
695 fsl,tuning-step= <2>;
696 bus-width = <4>;
700 sdma1: dma-controller@30bd0000 {
701 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
706 clock-names = "ipg", "ahb";
707 #dma-cells = <3>;
708 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
712 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
723 clock-names = "ipg", "ahb", "ptp",
725 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
729 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
732 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
733 fsl,num-tx-queues = <3>;
734 fsl,num-rx-queues = <3>;
739 gic: interrupt-controller@38800000 {
740 compatible = "arm,gic-v3";
743 #interrupt-cells = <3>;
744 interrupt-controller;
746 interrupt-parent = <&gic>;
749 ddr-pmu@3d800000 {
750 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";