Lines Matching +full:0 +full:x30380000
43 #size-cells = <0>;
45 A53_0: cpu@0 {
48 reg = <0x0>;
59 reg = <0x1>;
70 reg = <0x2>;
81 reg = <0x3>;
96 #clock-cells = <0>;
103 #clock-cells = <0>;
110 #clock-cells = <0>;
117 #clock-cells = <0>;
124 #clock-cells = <0>;
131 #clock-cells = <0>;
145 thermal-sensors = <&tmu 0>;
213 soc@0 {
217 ranges = <0x0 0x0 0x0 0x3e000000>;
221 reg = <0x30000000 0x400000>;
228 reg = <0x30200000 0x10000>;
236 gpio-ranges = <&iomuxc 0 5 30>;
241 reg = <0x30210000 0x10000>;
249 gpio-ranges = <&iomuxc 0 35 21>;
254 reg = <0x30220000 0x10000>;
262 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
267 reg = <0x30230000 0x10000>;
275 gpio-ranges = <&iomuxc 0 82 32>;
280 reg = <0x30240000 0x10000>;
288 gpio-ranges = <&iomuxc 0 114 30>;
293 reg = <0x30260000 0x10000>;
300 reg = <0x30280000 0x10000>;
308 reg = <0x30330000 0x10000>;
313 reg = <0x30340000 0x10000>;
318 reg = <0x30350000 0x10000>;
325 reg = <0x10 4>;
332 reg = <0x30360000 0x10000>;
336 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
337 reg = <0x30370000 0x10000>;
340 compatible = "fsl,sec-v4.0-mon-rtc-lp";
342 offset = <0x34>;
350 compatible = "fsl,sec-v4.0-pwrkey";
363 reg = <0x30380000 0x10000>;
386 assigned-clock-rates = <0>, <0>,
399 reg = <0x30390000 0x10000>;
407 reg = <0x30400000 0x400000>;
414 reg = <0x30660000 0x10000>;
425 reg = <0x30670000 0x10000>;
436 reg = <0x30680000 0x10000>;
447 reg = <0x30690000 0x10000>;
458 reg = <0x306a0000 0x20000>;
467 reg = <0x30800000 0x400000>;
474 #size-cells = <0>;
476 reg = <0x30820000 0x10000>;
481 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
488 #size-cells = <0>;
490 reg = <0x30830000 0x10000>;
502 #size-cells = <0>;
504 reg = <0x30840000 0x10000>;
516 reg = <0x30860000 0x10000>;
521 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
528 reg = <0x30880000 0x10000>;
533 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
540 reg = <0x30890000 0x10000>;
549 compatible = "fsl,sec-v4.0";
552 reg = <0x30900000 0x40000>;
553 ranges = <0 0x30900000 0x40000>;
560 compatible = "fsl,sec-v4.0-job-ring";
561 reg = <0x1000 0x1000>;
566 compatible = "fsl,sec-v4.0-job-ring";
567 reg = <0x2000 0x1000>;
572 compatible = "fsl,sec-v4.0-job-ring";
573 reg = <0x3000 0x1000>;
581 #size-cells = <0>;
582 reg = <0x30a20000 0x10000>;
591 #size-cells = <0>;
592 reg = <0x30a30000 0x10000>;
601 #size-cells = <0>;
602 reg = <0x30a40000 0x10000>;
611 #size-cells = <0>;
612 reg = <0x30a50000 0x10000>;
620 reg = <0x30a60000 0x10000>;
625 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
632 reg = <0x30aa0000 0x10000>;
641 #size-cells = <0>;
642 reg = <0x30ad0000 0x10000>;
651 #size-cells = <0>;
652 reg = <0x30ae0000 0x10000>;
660 reg = <0x30b40000 0x10000>;
674 reg = <0x30b50000 0x10000>;
688 reg = <0x30b60000 0x10000>;
702 reg = <0x30bd0000 0x10000>;
713 reg = <0x30be0000 0x10000>;
732 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
741 reg = <0x38800000 0x10000>,
742 <0x38880000 0xc0000>;
751 reg = <0x3d800000 0x400000>;