Lines Matching +full:imx51 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mn-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
43 #address-cells = <1>;
44 #size-cells = <0>;
46 idle-states {
47 entry-method = "psci";
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
61 compatible = "arm,cortex-a53";
63 clock-latency = <61036>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
71 #cooling-cells = <2>;
76 compatible = "arm,cortex-a53";
78 clock-latency = <61036>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
83 cpu-idle-states = <&cpu_pd_wait>;
84 #cooling-cells = <2>;
89 compatible = "arm,cortex-a53";
91 clock-latency = <61036>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
95 operating-points-v2 = <&a53_opp_table>;
96 cpu-idle-states = <&cpu_pd_wait>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a53";
104 clock-latency = <61036>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
108 operating-points-v2 = <&a53_opp_table>;
109 cpu-idle-states = <&cpu_pd_wait>;
110 #cooling-cells = <2>;
113 A53_L2: l2-cache0 {
118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <850000>;
125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
190 compatible = "arm,psci-1.0";
194 thermal-zones {
195 cpu-thermal {
196 polling-delay-passive = <250>;
197 polling-delay = <2000>;
198 thermal-sensors = <&tmu>;
213 cooling-maps {
216 cooling-device =
227 compatible = "arm,armv8-timer";
232 clock-frequency = <8000000>;
233 arm,no-tick-in-suspend;
237 compatible = "simple-bus";
238 #address-cells = <1>;
239 #size-cells = <1>;
243 compatible = "fsl,aips-bus", "simple-bus";
245 #address-cells = <1>;
246 #size-cells = <1>;
250 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 gpio-ranges = <&iomuxc 0 10 30>;
263 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
268 gpio-controller;
269 #gpio-cells = <2>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
272 gpio-ranges = <&iomuxc 0 40 21>;
276 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 gpio-ranges = <&iomuxc 0 61 26>;
289 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
294 gpio-controller;
295 #gpio-cells = <2>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 gpio-ranges = <&iomuxc 21 108 11>;
302 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 gpio-ranges = <&iomuxc 0 119 30>;
315 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
318 #thermal-sensor-cells = <0>;
322 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
330 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
338 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
345 sdma3: dma-controller@302b0000 {
346 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
351 clock-names = "ipg", "ahb";
352 #dma-cells = <3>;
353 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
356 sdma2: dma-controller@302c0000 {
357 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
362 clock-names = "ipg", "ahb";
363 #dma-cells = <3>;
364 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
368 compatible = "fsl,imx8mn-iomuxc";
372 gpr: iomuxc-gpr@30340000 {
373 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
378 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
381 #address-cells = <1>;
382 #size-cells = <1>;
384 cpu_speed_grade: speed-grade@10 {
390 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
396 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
399 snvs_rtc: snvs-rtc-lp {
400 compatible = "fsl,sec-v4.0-mon-rtc-lp";
406 clock-names = "snvs-rtc";
409 snvs_pwrkey: snvs-powerkey {
410 compatible = "fsl,sec-v4.0-pwrkey";
414 clock-names = "snvs-pwrkey";
416 wakeup-source;
421 clk: clock-controller@30380000 {
422 compatible = "fsl,imx8mn-ccm";
424 #clock-cells = <1>;
427 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
429 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
435 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
439 assigned-clock-rates = <0>, <0>, <0>,
445 src: reset-controller@30390000 {
446 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
449 #reset-cells = <1>;
454 compatible = "fsl,aips-bus", "simple-bus";
456 #address-cells = <1>;
457 #size-cells = <1>;
461 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
466 clock-names = "ipg", "per";
467 #pwm-cells = <2>;
472 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
477 clock-names = "ipg", "per";
478 #pwm-cells = <2>;
483 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
488 clock-names = "ipg", "per";
489 #pwm-cells = <2>;
494 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
499 clock-names = "ipg", "per";
500 #pwm-cells = <2>;
505 compatible = "nxp,sysctr-timer";
509 clock-names = "per";
514 compatible = "fsl,aips-bus", "simple-bus";
516 #address-cells = <1>;
517 #size-cells = <1>;
521 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
522 #address-cells = <1>;
523 #size-cells = <0>;
528 clock-names = "ipg", "per";
530 dma-names = "rx", "tx";
535 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
536 #address-cells = <1>;
537 #size-cells = <0>;
542 clock-names = "ipg", "per";
544 dma-names = "rx", "tx";
549 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
550 #address-cells = <1>;
551 #size-cells = <0>;
556 clock-names = "ipg", "per";
558 dma-names = "rx", "tx";
563 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
568 clock-names = "ipg", "per";
570 dma-names = "rx", "tx";
575 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
580 clock-names = "ipg", "per";
582 dma-names = "rx", "tx";
587 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
592 clock-names = "ipg", "per";
597 compatible = "fsl,sec-v4.0";
598 #address-cells = <1>;
599 #size-cells = <1>;
605 clock-names = "aclk", "ipg";
608 compatible = "fsl,sec-v4.0-job-ring";
614 compatible = "fsl,sec-v4.0-job-ring";
620 compatible = "fsl,sec-v4.0-job-ring";
626 i2c1: i2c@30a20000 {
627 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
628 #address-cells = <1>;
629 #size-cells = <0>;
636 i2c2: i2c@30a30000 {
637 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
638 #address-cells = <1>;
639 #size-cells = <0>;
646 i2c3: i2c@30a40000 {
647 #address-cells = <1>;
648 #size-cells = <0>;
649 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
656 i2c4: i2c@30a50000 {
657 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
658 #address-cells = <1>;
659 #size-cells = <0>;
667 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
672 clock-names = "ipg", "per";
674 dma-names = "rx", "tx";
679 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
683 #mbox-cells = <2>;
687 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
693 clock-names = "ipg", "ahb", "per";
694 fsl,tuning-start-tap = <20>;
695 fsl,tuning-step= <2>;
696 bus-width = <4>;
701 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
707 clock-names = "ipg", "ahb", "per";
708 fsl,tuning-start-tap = <20>;
709 fsl,tuning-step= <2>;
710 bus-width = <4>;
715 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
721 clock-names = "ipg", "ahb", "per";
722 fsl,tuning-start-tap = <20>;
723 fsl,tuning-step= <2>;
724 bus-width = <4>;
728 sdma1: dma-controller@30bd0000 {
729 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
734 clock-names = "ipg", "ahb";
735 #dma-cells = <3>;
736 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
740 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
751 clock-names = "ipg", "ahb", "ptp",
753 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
757 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
760 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
761 fsl,num-tx-queues = <3>;
762 fsl,num-rx-queues = <3>;
769 compatible = "fsl,aips-bus", "simple-bus";
771 #address-cells = <1>;
772 #size-cells = <1>;
776 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
780 clock-names = "usb1_ctrl_root_clk";
781 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
782 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
789 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
790 #index-cells = <1>;
795 dma_apbh: dma-controller@33000000 {
796 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
802 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
803 #dma-cells = <1>;
804 dma-channels = <4>;
808 gpmi: nand-controller@33002000 {
809 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
810 #address-cells = <1>;
811 #size-cells = <1>;
813 reg-names = "gpmi-nand", "bch";
815 interrupt-names = "bch";
818 clock-names = "gpmi_io", "gpmi_bch_apb";
820 dma-names = "rx-tx";
824 gic: interrupt-controller@38800000 {
825 compatible = "arm,gic-v3";
828 #interrupt-cells = <3>;
829 interrupt-controller;
833 ddrc: memory-controller@3d400000 {
834 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
836 clock-names = "core", "pll", "alt", "apb";
843 ddr-pmu@3d800000 {
844 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
851 compatible = "usb-nop-xceiv";
853 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
854 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
855 clock-names = "main_clk";