Lines Matching +full:0 +full:x30380000
44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xb00>, <0x7>;
133 opp-supported-hw = <0x300>, <0x7>;
141 opp-supported-hw = <0x100>, <0x3>;
149 #clock-cells = <0>;
156 #clock-cells = <0>;
163 #clock-cells = <0>;
170 #clock-cells = <0>;
177 #clock-cells = <0>;
184 #clock-cells = <0>;
236 soc@0 {
240 ranges = <0x0 0x0 0x0 0x3e000000>;
244 reg = <0x30000000 0x400000>;
251 reg = <0x30200000 0x10000>;
259 gpio-ranges = <&iomuxc 0 10 30>;
264 reg = <0x30210000 0x10000>;
272 gpio-ranges = <&iomuxc 0 40 21>;
277 reg = <0x30220000 0x10000>;
285 gpio-ranges = <&iomuxc 0 61 26>;
290 reg = <0x30230000 0x10000>;
303 reg = <0x30240000 0x10000>;
311 gpio-ranges = <&iomuxc 0 119 30>;
316 reg = <0x30260000 0x10000>;
318 #thermal-sensor-cells = <0>;
323 reg = <0x30280000 0x10000>;
331 reg = <0x30290000 0x10000>;
339 reg = <0x302a0000 0x10000>;
347 reg = <0x302b0000 0x10000>;
358 reg = <0x302c0000 0x10000>;
369 reg = <0x30330000 0x10000>;
374 reg = <0x30340000 0x10000>;
379 reg = <0x30350000 0x10000>;
385 reg = <0x10 4>;
392 reg = <0x30360000 0x10000>;
396 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
397 reg = <0x30370000 0x10000>;
400 compatible = "fsl,sec-v4.0-mon-rtc-lp";
402 offset = <0x34>;
410 compatible = "fsl,sec-v4.0-pwrkey";
423 reg = <0x30380000 0x10000>;
439 assigned-clock-rates = <0>, <0>, <0>,
447 reg = <0x30390000 0x10000>;
455 reg = <0x30400000 0x400000>;
462 reg = <0x30660000 0x10000>;
473 reg = <0x30670000 0x10000>;
484 reg = <0x30680000 0x10000>;
495 reg = <0x30690000 0x10000>;
506 reg = <0x306a0000 0x20000>;
515 reg = <0x30800000 0x400000>;
523 #size-cells = <0>;
524 reg = <0x30820000 0x10000>;
529 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
537 #size-cells = <0>;
538 reg = <0x30830000 0x10000>;
551 #size-cells = <0>;
552 reg = <0x30840000 0x10000>;
564 reg = <0x30860000 0x10000>;
569 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
576 reg = <0x30880000 0x10000>;
581 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
588 reg = <0x30890000 0x10000>;
597 compatible = "fsl,sec-v4.0";
600 reg = <0x30900000 0x40000>;
601 ranges = <0 0x30900000 0x40000>;
608 compatible = "fsl,sec-v4.0-job-ring";
609 reg = <0x1000 0x1000>;
614 compatible = "fsl,sec-v4.0-job-ring";
615 reg = <0x2000 0x1000>;
620 compatible = "fsl,sec-v4.0-job-ring";
621 reg = <0x3000 0x1000>;
629 #size-cells = <0>;
630 reg = <0x30a20000 0x10000>;
639 #size-cells = <0>;
640 reg = <0x30a30000 0x10000>;
648 #size-cells = <0>;
650 reg = <0x30a40000 0x10000>;
659 #size-cells = <0>;
660 reg = <0x30a50000 0x10000>;
668 reg = <0x30a60000 0x10000>;
673 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
680 reg = <0x30aa0000 0x10000>;
688 reg = <0x30b40000 0x10000>;
702 reg = <0x30b50000 0x10000>;
716 reg = <0x30b60000 0x10000>;
730 reg = <0x30bd0000 0x10000>;
741 reg = <0x30be0000 0x10000>;
760 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
770 reg = <0x32c00000 0x400000>;
777 reg = <0x32e40000 0x200>;
784 fsl,usbmisc = <&usbmisc1 0>;
791 reg = <0x32e40200 0x200>;
797 reg = <0x33000000 0x2000>;
812 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
819 dmas = <&dma_apbh 0>;
826 reg = <0x38800000 0x10000>,
827 <0x38880000 0xc0000>;
835 reg = <0x3d400000 0x400000>;
845 reg = <0x3d800000 0x400000>;