Lines Matching +full:imx51 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mm-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
43 #address-cells = <1>;
44 #size-cells = <0>;
46 idle-states {
47 entry-method = "psci";
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
61 compatible = "arm,cortex-a53";
63 clock-latency = <61036>; /* two CLK32 periods */
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
71 #cooling-cells = <2>;
76 compatible = "arm,cortex-a53";
78 clock-latency = <61036>; /* two CLK32 periods */
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
83 cpu-idle-states = <&cpu_pd_wait>;
84 #cooling-cells = <2>;
89 compatible = "arm,cortex-a53";
91 clock-latency = <61036>; /* two CLK32 periods */
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
95 operating-points-v2 = <&a53_opp_table>;
96 cpu-idle-states = <&cpu_pd_wait>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a53";
104 clock-latency = <61036>; /* two CLK32 periods */
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
108 operating-points-v2 = <&a53_opp_table>;
109 cpu-idle-states = <&cpu_pd_wait>;
110 #cooling-cells = <2>;
113 A53_L2: l2-cache0 {
118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <850000>;
125 opp-supported-hw = <0xe>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
130 opp-1600000000 {
131 opp-hz = /bits/ 64 <1600000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0xc>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
138 opp-1800000000 {
139 opp-hz = /bits/ 64 <1800000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x8>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
190 compatible = "arm,psci-1.0";
195 compatible = "arm,armv8-pmuv3";
198 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
202 compatible = "arm,armv8-timer";
204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
207 clock-frequency = <8000000>;
208 arm,no-tick-in-suspend;
211 thermal-zones {
212 cpu-thermal {
213 polling-delay-passive = <250>;
214 polling-delay = <2000>;
215 thermal-sensors = <&tmu>;
230 cooling-maps {
233 cooling-device =
244 compatible = "usb-nop-xceiv";
246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
248 clock-names = "main_clk";
252 compatible = "usb-nop-xceiv";
254 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
255 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
256 clock-names = "main_clk";
260 compatible = "simple-bus";
261 #address-cells = <1>;
262 #size-cells = <1>;
266 compatible = "fsl,aips-bus", "simple-bus";
268 #address-cells = <1>;
269 #size-cells = <1>;
273 #sound-dai-cells = <0>;
274 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
280 clock-names = "bus", "mclk1", "mclk2", "mclk3";
282 dma-names = "rx", "tx";
287 #sound-dai-cells = <0>;
288 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
294 clock-names = "bus", "mclk1", "mclk2", "mclk3";
296 dma-names = "rx", "tx";
301 #sound-dai-cells = <0>;
302 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
308 clock-names = "bus", "mclk1", "mclk2", "mclk3";
310 dma-names = "rx", "tx";
315 #sound-dai-cells = <0>;
316 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
322 clock-names = "bus", "mclk1", "mclk2", "mclk3";
324 dma-names = "rx", "tx";
329 #sound-dai-cells = <0>;
330 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
336 clock-names = "bus", "mclk1", "mclk2", "mclk3";
338 dma-names = "rx", "tx";
343 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 gpio-ranges = <&iomuxc 0 10 30>;
356 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
365 gpio-ranges = <&iomuxc 0 40 21>;
369 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 gpio-ranges = <&iomuxc 0 61 26>;
382 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
387 gpio-controller;
388 #gpio-cells = <2>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
391 gpio-ranges = <&iomuxc 0 87 32>;
395 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 gpio-ranges = <&iomuxc 0 119 30>;
408 compatible = "fsl,imx8mm-tmu";
411 #thermal-sensor-cells = <0>;
415 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
423 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
431 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
438 sdma2: dma-controller@302c0000 {
439 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
444 clock-names = "ipg", "ahb";
445 #dma-cells = <3>;
446 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
449 sdma3: dma-controller@302b0000 {
450 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
455 clock-names = "ipg", "ahb";
456 #dma-cells = <3>;
457 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
461 compatible = "fsl,imx8mm-iomuxc";
465 gpr: iomuxc-gpr@30340000 {
466 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
471 compatible = "fsl,imx8mm-ocotp", "syscon";
475 #address-cells = <1>;
476 #size-cells = <1>;
478 cpu_speed_grade: speed-grade@10 {
484 compatible = "fsl,imx8mm-anatop", "syscon";
489 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
492 snvs_rtc: snvs-rtc-lp {
493 compatible = "fsl,sec-v4.0-mon-rtc-lp";
499 clock-names = "snvs-rtc";
502 snvs_pwrkey: snvs-powerkey {
503 compatible = "fsl,sec-v4.0-pwrkey";
507 clock-names = "snvs-pwrkey";
509 wakeup-source;
514 clk: clock-controller@30380000 {
515 compatible = "fsl,imx8mm-ccm";
517 #clock-cells = <1>;
520 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
522 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
531 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
535 assigned-clock-rates = <0>, <0>, <0>,
544 src: reset-controller@30390000 {
545 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
548 #reset-cells = <1>;
553 compatible = "fsl,aips-bus", "simple-bus";
555 #address-cells = <1>;
556 #size-cells = <1>;
560 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
565 clock-names = "ipg", "per";
566 #pwm-cells = <2>;
571 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
576 clock-names = "ipg", "per";
577 #pwm-cells = <2>;
582 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
587 clock-names = "ipg", "per";
588 #pwm-cells = <2>;
593 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
598 clock-names = "ipg", "per";
599 #pwm-cells = <2>;
604 compatible = "nxp,sysctr-timer";
608 clock-names = "per";
613 compatible = "fsl,aips-bus", "simple-bus";
615 #address-cells = <1>;
616 #size-cells = <1>;
621 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
622 #address-cells = <1>;
623 #size-cells = <0>;
628 clock-names = "ipg", "per";
630 dma-names = "rx", "tx";
635 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
636 #address-cells = <1>;
637 #size-cells = <0>;
642 clock-names = "ipg", "per";
644 dma-names = "rx", "tx";
649 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
650 #address-cells = <1>;
651 #size-cells = <0>;
656 clock-names = "ipg", "per";
658 dma-names = "rx", "tx";
663 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
668 clock-names = "ipg", "per";
670 dma-names = "rx", "tx";
675 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
680 clock-names = "ipg", "per";
682 dma-names = "rx", "tx";
687 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
692 clock-names = "ipg", "per";
697 compatible = "fsl,sec-v4.0";
698 #address-cells = <1>;
699 #size-cells = <1>;
705 clock-names = "aclk", "ipg";
708 compatible = "fsl,sec-v4.0-job-ring";
714 compatible = "fsl,sec-v4.0-job-ring";
720 compatible = "fsl,sec-v4.0-job-ring";
726 i2c1: i2c@30a20000 {
727 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
728 #address-cells = <1>;
729 #size-cells = <0>;
736 i2c2: i2c@30a30000 {
737 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
738 #address-cells = <1>;
739 #size-cells = <0>;
746 i2c3: i2c@30a40000 {
747 #address-cells = <1>;
748 #size-cells = <0>;
749 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
756 i2c4: i2c@30a50000 {
757 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
758 #address-cells = <1>;
759 #size-cells = <0>;
767 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
772 clock-names = "ipg", "per";
774 dma-names = "rx", "tx";
779 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
783 #mbox-cells = <2>;
787 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
793 clock-names = "ipg", "ahb", "per";
794 fsl,tuning-start-tap = <20>;
795 fsl,tuning-step= <2>;
796 bus-width = <4>;
801 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
807 clock-names = "ipg", "ahb", "per";
808 fsl,tuning-start-tap = <20>;
809 fsl,tuning-step= <2>;
810 bus-width = <4>;
815 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
821 clock-names = "ipg", "ahb", "per";
822 fsl,tuning-start-tap = <20>;
823 fsl,tuning-step= <2>;
824 bus-width = <4>;
829 #address-cells = <1>;
830 #size-cells = <0>;
831 compatible = "nxp,imx8mm-fspi";
833 reg-names = "fspi_base", "fspi_mmap";
837 clock-names = "fspi", "fspi_en";
841 sdma1: dma-controller@30bd0000 {
842 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
847 clock-names = "ipg", "ahb";
848 #dma-cells = <3>;
849 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
853 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
864 clock-names = "ipg", "ahb", "ptp",
866 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
870 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
873 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
874 fsl,num-tx-queues = <3>;
875 fsl,num-rx-queues = <3>;
882 compatible = "fsl,aips-bus", "simple-bus";
884 #address-cells = <1>;
885 #size-cells = <1>;
889 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
893 clock-names = "usb1_ctrl_root_clk";
894 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
895 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
902 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
903 #index-cells = <1>;
908 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
912 clock-names = "usb1_ctrl_root_clk";
913 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
914 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
921 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
922 #index-cells = <1>;
928 dma_apbh: dma-controller@33000000 {
929 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
935 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
936 #dma-cells = <1>;
937 dma-channels = <4>;
941 gpmi: nand-controller@33002000{
942 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
943 #address-cells = <1>;
944 #size-cells = <1>;
946 reg-names = "gpmi-nand", "bch";
948 interrupt-names = "bch";
951 clock-names = "gpmi_io", "gpmi_bch_apb";
953 dma-names = "rx-tx";
957 gic: interrupt-controller@38800000 {
958 compatible = "arm,gic-v3";
961 #interrupt-cells = <3>;
962 interrupt-controller;
966 ddrc: memory-controller@3d400000 {
967 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
969 clock-names = "core", "pll", "alt", "apb";
976 ddr-pmu@3d800000 {
977 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";