Lines Matching +full:0 +full:x33000000
44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xe>, <0x7>;
133 opp-supported-hw = <0xc>, <0x7>;
141 opp-supported-hw = <0x8>, <0x3>;
149 #clock-cells = <0>;
156 #clock-cells = <0>;
163 #clock-cells = <0>;
170 #clock-cells = <0>;
177 #clock-cells = <0>;
184 #clock-cells = <0>;
259 soc@0 {
263 ranges = <0x0 0x0 0x0 0x3e000000>;
267 reg = <0x30000000 0x400000>;
270 ranges = <0x30000000 0x30000000 0x400000>;
273 #sound-dai-cells = <0>;
275 reg = <0x30010000 0x10000>;
281 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
287 #sound-dai-cells = <0>;
289 reg = <0x30020000 0x10000>;
295 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
301 #sound-dai-cells = <0>;
303 reg = <0x30030000 0x10000>;
309 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
315 #sound-dai-cells = <0>;
317 reg = <0x30050000 0x10000>;
323 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
329 #sound-dai-cells = <0>;
331 reg = <0x30060000 0x10000>;
337 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
344 reg = <0x30200000 0x10000>;
352 gpio-ranges = <&iomuxc 0 10 30>;
357 reg = <0x30210000 0x10000>;
365 gpio-ranges = <&iomuxc 0 40 21>;
370 reg = <0x30220000 0x10000>;
378 gpio-ranges = <&iomuxc 0 61 26>;
383 reg = <0x30230000 0x10000>;
391 gpio-ranges = <&iomuxc 0 87 32>;
396 reg = <0x30240000 0x10000>;
404 gpio-ranges = <&iomuxc 0 119 30>;
409 reg = <0x30260000 0x10000>;
411 #thermal-sensor-cells = <0>;
416 reg = <0x30280000 0x10000>;
424 reg = <0x30290000 0x10000>;
432 reg = <0x302a0000 0x10000>;
440 reg = <0x302c0000 0x10000>;
451 reg = <0x302b0000 0x10000>;
462 reg = <0x30330000 0x10000>;
467 reg = <0x30340000 0x10000>;
472 reg = <0x30350000 0x10000>;
479 reg = <0x10 4>;
485 reg = <0x30360000 0x10000>;
489 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
490 reg = <0x30370000 0x10000>;
493 compatible = "fsl,sec-v4.0-mon-rtc-lp";
495 offset = <0x34>;
503 compatible = "fsl,sec-v4.0-pwrkey";
516 reg = <0x30380000 0x10000>;
535 assigned-clock-rates = <0>, <0>, <0>,
546 reg = <0x30390000 0x10000>;
554 reg = <0x30400000 0x400000>;
557 ranges = <0x30400000 0x30400000 0x400000>;
561 reg = <0x30660000 0x10000>;
572 reg = <0x30670000 0x10000>;
583 reg = <0x30680000 0x10000>;
594 reg = <0x30690000 0x10000>;
605 reg = <0x306a0000 0x20000>;
614 reg = <0x30800000 0x400000>;
617 ranges = <0x30800000 0x30800000 0x400000>,
618 <0x8000000 0x8000000 0x10000000>;
623 #size-cells = <0>;
624 reg = <0x30820000 0x10000>;
629 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
637 #size-cells = <0>;
638 reg = <0x30830000 0x10000>;
651 #size-cells = <0>;
652 reg = <0x30840000 0x10000>;
664 reg = <0x30860000 0x10000>;
669 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
676 reg = <0x30880000 0x10000>;
681 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
688 reg = <0x30890000 0x10000>;
697 compatible = "fsl,sec-v4.0";
700 reg = <0x30900000 0x40000>;
701 ranges = <0 0x30900000 0x40000>;
708 compatible = "fsl,sec-v4.0-job-ring";
709 reg = <0x1000 0x1000>;
714 compatible = "fsl,sec-v4.0-job-ring";
715 reg = <0x2000 0x1000>;
720 compatible = "fsl,sec-v4.0-job-ring";
721 reg = <0x3000 0x1000>;
729 #size-cells = <0>;
730 reg = <0x30a20000 0x10000>;
739 #size-cells = <0>;
740 reg = <0x30a30000 0x10000>;
748 #size-cells = <0>;
750 reg = <0x30a40000 0x10000>;
759 #size-cells = <0>;
760 reg = <0x30a50000 0x10000>;
768 reg = <0x30a60000 0x10000>;
773 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
780 reg = <0x30aa0000 0x10000>;
788 reg = <0x30b40000 0x10000>;
802 reg = <0x30b50000 0x10000>;
816 reg = <0x30b60000 0x10000>;
830 #size-cells = <0>;
832 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
843 reg = <0x30bd0000 0x10000>;
854 reg = <0x30be0000 0x10000>;
873 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
883 reg = <0x32c00000 0x400000>;
886 ranges = <0x32c00000 0x32c00000 0x400000>;
890 reg = <0x32e40000 0x200>;
897 fsl,usbmisc = <&usbmisc1 0>;
904 reg = <0x32e40200 0x200>;
909 reg = <0x32e50000 0x200>;
916 fsl,usbmisc = <&usbmisc2 0>;
923 reg = <0x32e50200 0x200>;
930 reg = <0x33000000 0x2000>;
945 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
952 dmas = <&dma_apbh 0>;
959 reg = <0x38800000 0x10000>, /* GIC Dist */
960 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
968 reg = <0x3d400000 0x400000>;
978 reg = <0x3d800000 0x400000>;