Lines Matching +full:non +full:- +full:prefetchable
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a57";
30 cpu-idle-states = <&CPU_PW20>;
31 next-level-cache = <&cluster0_l2>;
32 #cooling-cells = <2>;
37 compatible = "arm,cortex-a57";
40 cpu-idle-states = <&CPU_PW20>;
41 next-level-cache = <&cluster1_l2>;
42 #cooling-cells = <2>;
47 compatible = "arm,cortex-a57";
50 cpu-idle-states = <&CPU_PW20>;
51 next-level-cache = <&cluster1_l2>;
52 #cooling-cells = <2>;
57 compatible = "arm,cortex-a57";
60 cpu-idle-states = <&CPU_PW20>;
61 next-level-cache = <&cluster2_l2>;
62 #cooling-cells = <2>;
67 compatible = "arm,cortex-a57";
70 cpu-idle-states = <&CPU_PW20>;
71 next-level-cache = <&cluster2_l2>;
72 #cooling-cells = <2>;
77 compatible = "arm,cortex-a57";
80 next-level-cache = <&cluster3_l2>;
81 cpu-idle-states = <&CPU_PW20>;
82 #cooling-cells = <2>;
87 compatible = "arm,cortex-a57";
90 cpu-idle-states = <&CPU_PW20>;
91 next-level-cache = <&cluster3_l2>;
92 #cooling-cells = <2>;
95 cluster0_l2: l2-cache0 {
99 cluster1_l2: l2-cache1 {
103 cluster2_l2: l2-cache2 {
107 cluster3_l2: l2-cache3 {
111 CPU_PW20: cpu-pw20 {
112 compatible = "arm,idle-state";
113 idle-state-name = "PW20";
114 arm,psci-suspend-param = <0x00010000>;
115 entry-latency-us = <2000>;
116 exit-latency-us = <2000>;
117 min-residency-us = <6000>;
126 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
134 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
142 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
150 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */