Lines Matching +full:0 +full:x00010000
15 cpu0: cpu@0 {
18 reg = <0x0>;
19 clocks = <&clockgen 1 0>;
28 reg = <0x1>;
29 clocks = <&clockgen 1 0>;
38 reg = <0x100>;
48 reg = <0x101>;
58 reg = <0x200>;
68 reg = <0x201>;
78 reg = <0x300>;
88 reg = <0x301>;
114 arm,psci-suspend-param = <0x00010000>;
122 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
123 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
125 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
126 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
130 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
131 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
133 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
134 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
138 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
139 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
141 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
142 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
146 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
147 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
149 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
150 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */