Lines Matching +full:gic +full:- +full:its
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 /* We have 2 clusters having 4 Cortex-A53 cores each */
31 compatible = "arm,cortex-a53";
34 cpu-idle-states = <&CPU_PH20>;
35 #cooling-cells = <2>;
40 compatible = "arm,cortex-a53";
43 cpu-idle-states = <&CPU_PH20>;
44 #cooling-cells = <2>;
49 compatible = "arm,cortex-a53";
52 cpu-idle-states = <&CPU_PH20>;
53 #cooling-cells = <2>;
58 compatible = "arm,cortex-a53";
61 cpu-idle-states = <&CPU_PH20>;
62 #cooling-cells = <2>;
67 compatible = "arm,cortex-a53";
70 cpu-idle-states = <&CPU_PH20>;
71 #cooling-cells = <2>;
76 compatible = "arm,cortex-a53";
79 cpu-idle-states = <&CPU_PH20>;
80 #cooling-cells = <2>;
85 compatible = "arm,cortex-a53";
88 cpu-idle-states = <&CPU_PH20>;
89 #cooling-cells = <2>;
94 compatible = "arm,cortex-a53";
97 cpu-idle-states = <&CPU_PH20>;
98 #cooling-cells = <2>;
101 CPU_PH20: cpu-ph20 {
102 compatible = "arm,idle-state";
103 idle-state-name = "PH20";
104 arm,psci-suspend-param = <0x0>;
105 entry-latency-us = <1000>;
106 exit-latency-us = <1000>;
107 min-residency-us = <3000>;
111 gic: interrupt-controller@6000000 { label
112 compatible = "arm,gic-v3";
113 #interrupt-cells = <3>;
114 interrupt-controller;
115 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
121 #address-cells = <2>;
122 #size-cells = <2>;
125 its: gic-its@6020000 { label
126 compatible = "arm,gic-v3-its";
127 msi-controller;
132 thermal-zones {
133 core-cluster {
134 polling-delay-passive = <1000>;
135 polling-delay = <5000>;
136 thermal-sensors = <&tmu 0>;
139 core_cluster_alert: core-cluster-alert {
145 core-cluster-crit {
152 cooling-maps {
155 cooling-device =
169 polling-delay-passive = <1000>;
170 polling-delay = <5000>;
171 thermal-sensors = <&tmu 1>;
174 soc-crit {
184 compatible = "arm,armv8-timer";
186 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
192 compatible = "arm,psci-0.2";
197 compatible = "fixed-clock";
198 #clock-cells = <0>;
199 clock-frequency = <100000000>;
200 clock-output-names = "sysclk";
204 compatible = "simple-bus";
205 #address-cells = <2>;
206 #size-cells = <2>;
208 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
211 compatible = "fsl,ls1088a-clockgen";
213 #clock-cells = <2>;
218 compatible = "fsl,ls1088a-dcfg", "syscon";
220 little-endian;
224 compatible = "fsl,qoriq-tmu";
227 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
228 fsl,tmu-calibration =
270 little-endian;
271 #thermal-sensor-cells = <1>;
275 compatible = "fsl,ls1088a-dspi",
276 "fsl,ls1021a-v1.0-dspi";
277 #address-cells = <1>;
278 #size-cells = <0>;
281 clock-names = "dspi";
283 spi-num-chipselects = <6>;
304 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
307 little-endian;
308 gpio-controller;
309 #gpio-cells = <2>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
315 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
318 little-endian;
319 gpio-controller;
320 #gpio-cells = <2>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
326 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
329 little-endian;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
337 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
340 little-endian;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
348 compatible = "fsl,ifc", "simple-bus";
351 little-endian;
352 #address-cells = <2>;
353 #size-cells = <1>;
358 compatible = "fsl,vf610-i2c";
359 #address-cells = <1>;
360 #size-cells = <0>;
368 compatible = "fsl,vf610-i2c";
369 #address-cells = <1>;
370 #size-cells = <0>;
378 compatible = "fsl,vf610-i2c";
379 #address-cells = <1>;
380 #size-cells = <0>;
388 compatible = "fsl,vf610-i2c";
389 #address-cells = <1>;
390 #size-cells = <0>;
398 compatible = "fsl,ls2080a-qspi";
399 #address-cells = <1>;
400 #size-cells = <0>;
403 reg-names = "QuadSPI", "QuadSPI-memory";
405 clock-names = "qspi_en", "qspi";
411 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
414 clock-frequency = <0>;
416 voltage-ranges = <1800 1800 3300 3300>;
417 sdhci,auto-cmd12;
418 little-endian;
419 bus-width = <4>;
428 snps,quirk-frame-length-adjustment = <0x20>;
430 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
439 snps,quirk-frame-length-adjustment = <0x20>;
445 compatible = "fsl,ls1088a-ahci";
448 reg-names = "ahci", "sata-ecc";
451 dma-coherent;
456 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
457 fsl,sec-era = <8>;
458 #address-cells = <1>;
459 #size-cells = <1>;
463 dma-coherent;
466 compatible = "fsl,sec-v5.0-job-ring",
467 "fsl,sec-v4.0-job-ring";
473 compatible = "fsl,sec-v5.0-job-ring",
474 "fsl,sec-v4.0-job-ring";
480 compatible = "fsl,sec-v5.0-job-ring",
481 "fsl,sec-v4.0-job-ring";
487 compatible = "fsl,sec-v5.0-job-ring",
488 "fsl,sec-v4.0-job-ring";
495 compatible = "fsl,ls1088a-pcie";
498 reg-names = "regs", "config";
500 interrupt-names = "aer";
501 #address-cells = <3>;
502 #size-cells = <2>;
504 dma-coherent;
505 num-viewport = <256>;
506 bus-range = <0x0 0xff>;
508 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
509 msi-parent = <&its>;
510 #interrupt-cells = <1>;
511 interrupt-map-mask = <0 0 0 7>;
512 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
513 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
514 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
515 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
516 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
521 compatible = "fsl,ls1088a-pcie";
524 reg-names = "regs", "config";
526 interrupt-names = "aer";
527 #address-cells = <3>;
528 #size-cells = <2>;
530 dma-coherent;
531 num-viewport = <6>;
532 bus-range = <0x0 0xff>;
534 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
535 msi-parent = <&its>;
536 #interrupt-cells = <1>;
537 interrupt-map-mask = <0 0 0 7>;
538 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
539 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
540 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
541 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
542 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
547 compatible = "fsl,ls1088a-pcie";
550 reg-names = "regs", "config";
552 interrupt-names = "aer";
553 #address-cells = <3>;
554 #size-cells = <2>;
556 dma-coherent;
557 num-viewport = <6>;
558 bus-range = <0x0 0xff>;
560 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
561 msi-parent = <&its>;
562 #interrupt-cells = <1>;
563 interrupt-map-mask = <0 0 0 7>;
564 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
565 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
566 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
567 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
568 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
573 compatible = "arm,mmu-500";
575 #iommu-cells = <1>;
576 stream-match-mask = <0x7C00>;
577 #global-interrupts = <12>;
582 // global non-secure fault
584 // combined non-secure
586 // performance counter interrupts 0-7
663 compatible = "fsl,dpaa2-console";
667 ptp-timer@8b95000 {
668 compatible = "fsl,dpaa2-ptp";
671 little-endian;
672 fsl,extts-fifo;
676 compatible = "arm,sp805-wdt", "arm,primecell";
679 clock-names = "wdog_clk", "apb_pclk";
683 compatible = "arm,sp805-wdt", "arm,primecell";
686 clock-names = "wdog_clk", "apb_pclk";
690 compatible = "arm,sp805-wdt", "arm,primecell";
693 clock-names = "wdog_clk", "apb_pclk";
697 compatible = "arm,sp805-wdt", "arm,primecell";
700 clock-names = "wdog_clk", "apb_pclk";
704 compatible = "arm,sp805-wdt", "arm,primecell";
707 clock-names = "wdog_clk", "apb_pclk";
711 compatible = "arm,sp805-wdt", "arm,primecell";
714 clock-names = "wdog_clk", "apb_pclk";
718 compatible = "arm,sp805-wdt", "arm,primecell";
721 clock-names = "wdog_clk", "apb_pclk";
725 compatible = "arm,sp805-wdt", "arm,primecell";
728 clock-names = "wdog_clk", "apb_pclk";
731 fsl_mc: fsl-mc@80c000000 {
732 compatible = "fsl,qoriq-mc";
735 msi-parent = <&its>;
736 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
737 dma-coherent;
738 #address-cells = <3>;
739 #size-cells = <1>;
742 * Region type 0x0 - MC portals
743 * Region type 0x1 - QBMAN portals
749 #address-cells = <1>;
750 #size-cells = <0>;
753 compatible = "fsl,qoriq-mc-dpmac";
758 compatible = "fsl,qoriq-mc-dpmac";
763 compatible = "fsl,qoriq-mc-dpmac";
768 compatible = "fsl,qoriq-mc-dpmac";
773 compatible = "fsl,qoriq-mc-dpmac";
778 compatible = "fsl,qoriq-mc-dpmac";
783 compatible = "fsl,qoriq-mc-dpmac";
788 compatible = "fsl,qoriq-mc-dpmac";
793 compatible = "fsl,qoriq-mc-dpmac";
798 compatible = "fsl,qoriq-mc-dpmac";
804 rcpm: power-controller@1e34040 {
805 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
807 #fsl,rcpm-wakeup-cells = <6>;
808 little-endian;
812 compatible = "fsl,ls1088a-ftm-alarm";
814 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
821 compatible = "linaro,optee-tz";