Lines Matching +full:0 +full:x5000000
26 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
41 reg = <0x1>;
42 clocks = <&clockgen 1 0>;
50 reg = <0x2>;
51 clocks = <&clockgen 1 0>;
59 reg = <0x3>;
60 clocks = <&clockgen 1 0>;
68 reg = <0x100>;
77 reg = <0x101>;
86 reg = <0x102>;
95 reg = <0x103>;
104 arm,psci-suspend-param = <0x0>;
115 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
116 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
117 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
118 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
119 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
128 reg = <0x0 0x6020000 0 0x20000>;
136 thermal-sensors = <&tmu 0>;
198 #clock-cells = <0>;
208 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
212 reg = <0 0x1300000 0 0xa0000>;
219 reg = <0x0 0x1e00000 0x0 0x10000>;
225 reg = <0x0 0x1f80000 0x0 0x10000>;
226 interrupts = <0 23 0x4>;
227 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
230 <0x00000000 0x00000023
231 0x00000001 0x0000002a
232 0x00000002 0x00000030
233 0x00000003 0x00000037
234 0x00000004 0x0000003d
235 0x00000005 0x00000044
236 0x00000006 0x0000004a
237 0x00000007 0x00000051
238 0x00000008 0x00000057
239 0x00000009 0x0000005e
240 0x0000000a 0x00000064
241 0x0000000b 0x0000006b
243 0x00010000 0x00000022
244 0x00010001 0x0000002a
245 0x00010002 0x00000032
246 0x00010003 0x0000003a
247 0x00010004 0x00000042
248 0x00010005 0x0000004a
249 0x00010006 0x00000052
250 0x00010007 0x0000005a
251 0x00010008 0x00000062
252 0x00010009 0x0000006a
254 0x00020000 0x00000021
255 0x00020001 0x0000002b
256 0x00020002 0x00000035
257 0x00020003 0x00000040
258 0x00020004 0x0000004a
259 0x00020005 0x00000054
260 0x00020006 0x0000005e
262 0x00030000 0x00000010
263 0x00030001 0x0000001c
264 0x00030002 0x00000027
265 0x00030003 0x00000032
266 0x00030004 0x0000003e
267 0x00030005 0x00000049
268 0x00030006 0x00000054
269 0x00030007 0x00000060>;
276 "fsl,ls1021a-v1.0-dspi";
278 #size-cells = <0>;
279 reg = <0x0 0x2100000 0x0 0x10000>;
289 reg = <0x0 0x21c0500 0x0 0x100>;
291 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
297 reg = <0x0 0x21c0600 0x0 0x100>;
299 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
305 reg = <0x0 0x2300000 0x0 0x10000>;
306 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
316 reg = <0x0 0x2310000 0x0 0x10000>;
317 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
327 reg = <0x0 0x2320000 0x0 0x10000>;
328 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
338 reg = <0x0 0x2330000 0x0 0x10000>;
339 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
349 reg = <0x0 0x2240000 0x0 0x20000>;
350 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
360 #size-cells = <0>;
361 reg = <0x0 0x2000000 0x0 0x10000>;
362 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
370 #size-cells = <0>;
371 reg = <0x0 0x2010000 0x0 0x10000>;
372 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
380 #size-cells = <0>;
381 reg = <0x0 0x2020000 0x0 0x10000>;
382 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
390 #size-cells = <0>;
391 reg = <0x0 0x2030000 0x0 0x10000>;
392 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
400 #size-cells = <0>;
401 reg = <0x0 0x20c0000 0x0 0x10000>,
402 <0x0 0x20000000 0x0 0x10000000>;
412 reg = <0x0 0x2140000 0x0 0x10000>;
413 interrupts = <0 28 0x4>; /* Level high type */
414 clock-frequency = <0>;
425 reg = <0x0 0x3100000 0x0 0x10000>;
426 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
428 snps,quirk-frame-length-adjustment = <0x20>;
436 reg = <0x0 0x3110000 0x0 0x10000>;
437 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
439 snps,quirk-frame-length-adjustment = <0x20>;
446 reg = <0x0 0x3200000 0x0 0x10000>,
447 <0x7 0x100520 0x0 0x4>;
449 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
456 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
460 ranges = <0x0 0x00 0x8000000 0x100000>;
461 reg = <0x00 0x8000000 0x0 0x100000>;
466 compatible = "fsl,sec-v5.0-job-ring",
467 "fsl,sec-v4.0-job-ring";
468 reg = <0x10000 0x10000>;
473 compatible = "fsl,sec-v5.0-job-ring",
474 "fsl,sec-v4.0-job-ring";
475 reg = <0x20000 0x10000>;
480 compatible = "fsl,sec-v5.0-job-ring",
481 "fsl,sec-v4.0-job-ring";
482 reg = <0x30000 0x10000>;
487 compatible = "fsl,sec-v5.0-job-ring",
488 "fsl,sec-v4.0-job-ring";
489 reg = <0x40000 0x10000>;
496 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
497 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
499 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
506 bus-range = <0x0 0xff>;
507 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
508 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
511 interrupt-map-mask = <0 0 0 7>;
512 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
513 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
514 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
515 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
516 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
522 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
523 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
525 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
532 bus-range = <0x0 0xff>;
533 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
534 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
537 interrupt-map-mask = <0 0 0 7>;
538 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
539 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
540 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
541 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
542 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
548 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
549 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
551 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
558 bus-range = <0x0 0xff>;
559 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
560 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
563 interrupt-map-mask = <0 0 0 7>;
564 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
565 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
566 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
567 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
568 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
574 reg = <0 0x5000000 0 0x800000>;
576 stream-match-mask = <0x7C00>;
586 // performance counter interrupts 0-7
664 reg = <0x00000000 0x08340020 0 0x2>;
669 reg = <0x0 0x8b95000 0x0 0x100>;
670 clocks = <&clockgen 4 0>;
677 reg = <0x0 0xc000000 0x0 0x1000>;
684 reg = <0x0 0xc010000 0x0 0x1000>;
691 reg = <0x0 0xc020000 0x0 0x1000>;
698 reg = <0x0 0xc030000 0x0 0x1000>;
705 reg = <0x0 0xc100000 0x0 0x1000>;
712 reg = <0x0 0xc110000 0x0 0x1000>;
719 reg = <0x0 0xc120000 0x0 0x1000>;
726 reg = <0x0 0xc130000 0x0 0x1000>;
733 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
734 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
736 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
742 * Region type 0x0 - MC portals
743 * Region type 0x1 - QBMAN portals
745 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
746 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
750 #size-cells = <0>;
799 reg = <0xa>;
806 reg = <0x0 0x1e34040 0x0 0x18>;
813 reg = <0x0 0x2800000 0x0 0x10000>;
814 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;