Lines Matching +full:vf610 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a72";
43 next-level-cache = <&l2>;
44 cpu-idle-states = <&CPU_PH20>;
45 #cooling-cells = <2>;
50 compatible = "arm,cortex-a72";
53 next-level-cache = <&l2>;
54 cpu-idle-states = <&CPU_PH20>;
55 #cooling-cells = <2>;
60 compatible = "arm,cortex-a72";
63 next-level-cache = <&l2>;
64 cpu-idle-states = <&CPU_PH20>;
65 #cooling-cells = <2>;
70 compatible = "arm,cortex-a72";
73 next-level-cache = <&l2>;
74 cpu-idle-states = <&CPU_PH20>;
75 #cooling-cells = <2>;
78 l2: l2-cache {
83 idle-states {
85 * PSCI node is not added default, U-boot will add missing
88 entry-method = "psci";
90 CPU_PH20: cpu-ph20 {
91 compatible = "arm,idle-state";
92 idle-state-name = "PH20";
93 arm,psci-suspend-param = <0x0>;
94 entry-latency-us = <1000>;
95 exit-latency-us = <1000>;
96 min-residency-us = <3000>;
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <100000000>;
110 clock-output-names = "sysclk";
114 compatible ="syscon-reboot";
120 thermal-zones {
121 ddr-controller {
122 polling-delay-passive = <1000>;
123 polling-delay = <5000>;
124 thermal-sensors = <&tmu 0>;
127 ddr-ctrler-alert {
133 ddr-ctrler-crit {
142 polling-delay-passive = <1000>;
143 polling-delay = <5000>;
144 thermal-sensors = <&tmu 1>;
147 serdes-alert {
153 serdes-crit {
162 polling-delay-passive = <1000>;
163 polling-delay = <5000>;
164 thermal-sensors = <&tmu 2>;
167 fman-alert {
173 fman-crit {
181 core-cluster {
182 polling-delay-passive = <1000>;
183 polling-delay = <5000>;
184 thermal-sensors = <&tmu 3>;
187 core_cluster_alert: core-cluster-alert {
193 core_cluster_crit: core-cluster-crit {
200 cooling-maps {
203 cooling-device =
213 polling-delay-passive = <1000>;
214 polling-delay = <5000>;
215 thermal-sensors = <&tmu 4>;
218 sec-alert {
224 sec-crit {
234 compatible = "arm,armv8-timer";
246 compatible = "arm,cortex-a72-pmu";
251 interrupt-affinity = <&cpu0>,
257 gic: interrupt-controller@1400000 {
258 compatible = "arm,gic-400";
259 #interrupt-cells = <3>;
260 interrupt-controller;
270 compatible = "simple-bus";
271 #address-cells = <2>;
272 #size-cells = <2>;
275 ddr: memory-controller@1080000 {
276 compatible = "fsl,qoriq-memory-controller";
279 big-endian;
283 compatible = "fsl,ifc", "simple-bus";
290 compatible = "fsl,ls1021a-qspi";
291 #address-cells = <1>;
292 #size-cells = <0>;
295 reg-names = "QuadSPI", "QuadSPI-memory";
297 clock-names = "qspi_en", "qspi";
303 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
307 voltage-ranges = <1800 1800 3300 3300>;
308 sdhci,auto-cmd12;
309 big-endian;
310 bus-width = <4>;
314 compatible = "fsl,ls1046a-scfg", "syscon";
316 big-endian;
320 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
321 "fsl,sec-v4.0";
322 fsl,sec-era = <8>;
323 #address-cells = <1>;
324 #size-cells = <1>;
330 compatible = "fsl,sec-v5.4-job-ring",
331 "fsl,sec-v5.0-job-ring",
332 "fsl,sec-v4.0-job-ring";
338 compatible = "fsl,sec-v5.4-job-ring",
339 "fsl,sec-v5.0-job-ring",
340 "fsl,sec-v4.0-job-ring";
346 compatible = "fsl,sec-v5.4-job-ring",
347 "fsl,sec-v5.0-job-ring",
348 "fsl,sec-v4.0-job-ring";
354 compatible = "fsl,sec-v5.4-job-ring",
355 "fsl,sec-v5.0-job-ring",
356 "fsl,sec-v4.0-job-ring";
366 memory-region = <&qman_fqd &qman_pfdr>;
374 memory-region = <&bman_fbpr>;
378 qportals: qman-portals@500000000 {
382 bportals: bman-portals@508000000 {
387 compatible = "fsl,ls1046a-dcfg", "syscon";
389 big-endian;
393 compatible = "fsl,ls1046a-clockgen";
395 #clock-cells = <2>;
400 compatible = "fsl,qoriq-tmu";
403 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
404 fsl,tmu-calibration =
442 big-endian;
443 #thermal-sensor-cells = <1>;
447 compatible = "fsl,ls1021a-v1.0-dspi";
448 #address-cells = <1>;
449 #size-cells = <0>;
452 clock-names = "dspi";
454 spi-num-chipselects = <5>;
455 big-endian;
459 i2c0: i2c@2180000 {
460 compatible = "fsl,vf610-i2c";
461 #address-cells = <1>;
462 #size-cells = <0>;
468 dma-names = "tx", "rx";
472 i2c1: i2c@2190000 {
473 compatible = "fsl,vf610-i2c";
474 #address-cells = <1>;
475 #size-cells = <0>;
482 i2c2: i2c@21a0000 {
483 compatible = "fsl,vf610-i2c";
484 #address-cells = <1>;
485 #size-cells = <0>;
492 i2c3: i2c@21b0000 {
493 compatible = "fsl,vf610-i2c";
494 #address-cells = <1>;
495 #size-cells = <0>;
535 compatible = "fsl,qoriq-gpio";
538 gpio-controller;
539 #gpio-cells = <2>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
545 compatible = "fsl,qoriq-gpio";
548 gpio-controller;
549 #gpio-cells = <2>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
555 compatible = "fsl,qoriq-gpio";
558 gpio-controller;
559 #gpio-cells = <2>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
565 compatible = "fsl,qoriq-gpio";
568 gpio-controller;
569 #gpio-cells = <2>;
570 interrupt-controller;
571 #interrupt-cells = <2>;
575 compatible = "fsl,ls1021a-lpuart";
579 clock-names = "ipg";
584 compatible = "fsl,ls1021a-lpuart";
588 clock-names = "ipg";
593 compatible = "fsl,ls1021a-lpuart";
597 clock-names = "ipg";
602 compatible = "fsl,ls1021a-lpuart";
606 clock-names = "ipg";
611 compatible = "fsl,ls1021a-lpuart";
615 clock-names = "ipg";
620 compatible = "fsl,ls1021a-lpuart";
624 clock-names = "ipg";
629 compatible = "fsl,imx21-wdt";
633 big-endian;
637 #dma-cells = <2>;
638 compatible = "fsl,vf610-edma";
644 interrupt-names = "edma-tx", "edma-err";
645 dma-channels = <32>;
646 big-endian;
647 clock-names = "dmamux0", "dmamux1";
657 snps,quirk-frame-length-adjustment = <0x20>;
659 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
667 snps,quirk-frame-length-adjustment = <0x20>;
669 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
677 snps,quirk-frame-length-adjustment = <0x20>;
679 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
683 compatible = "fsl,ls1046a-ahci";
686 reg-names = "ahci", "sata-ecc";
691 msi1: msi-controller@1580000 {
692 compatible = "fsl,ls1046a-msi";
693 msi-controller;
701 msi2: msi-controller@1590000 {
702 compatible = "fsl,ls1046a-msi";
703 msi-controller;
711 msi3: msi-controller@15a0000 {
712 compatible = "fsl,ls1046a-msi";
713 msi-controller;
722 compatible = "fsl,ls1046a-pcie";
725 reg-names = "regs", "config";
728 interrupt-names = "aer", "pme";
729 #address-cells = <3>;
730 #size-cells = <2>;
732 dma-coherent;
733 num-viewport = <8>;
734 bus-range = <0x0 0xff>;
736 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
737 msi-parent = <&msi1>, <&msi2>, <&msi3>;
738 #interrupt-cells = <1>;
739 interrupt-map-mask = <0 0 0 7>;
740 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
748 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
751 reg-names = "regs", "addr_space";
752 num-ib-windows = <6>;
753 num-ob-windows = <8>;
758 compatible = "fsl,ls1046a-pcie";
761 reg-names = "regs", "config";
764 interrupt-names = "aer", "pme";
765 #address-cells = <3>;
766 #size-cells = <2>;
768 dma-coherent;
769 num-viewport = <8>;
770 bus-range = <0x0 0xff>;
772 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
773 msi-parent = <&msi2>, <&msi3>, <&msi1>;
774 #interrupt-cells = <1>;
775 interrupt-map-mask = <0 0 0 7>;
776 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
784 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
787 reg-names = "regs", "addr_space";
788 num-ib-windows = <6>;
789 num-ob-windows = <8>;
794 compatible = "fsl,ls1046a-pcie";
797 reg-names = "regs", "config";
800 interrupt-names = "aer", "pme";
801 #address-cells = <3>;
802 #size-cells = <2>;
804 dma-coherent;
805 num-viewport = <8>;
806 bus-range = <0x0 0xff>;
808 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
809 msi-parent = <&msi3>, <&msi1>, <&msi2>;
810 #interrupt-cells = <1>;
811 interrupt-map-mask = <0 0 0 7>;
812 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
820 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
823 reg-names = "regs", "addr_space";
824 num-ib-windows = <6>;
825 num-ob-windows = <8>;
829 qdma: dma-controller@8380000 {
830 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
839 interrupt-names = "qdma-error", "qdma-queue0",
840 "qdma-queue1", "qdma-queue2", "qdma-queue3";
841 dma-channels = <8>;
842 block-number = <1>;
843 block-offset = <0x10000>;
844 fsl,dma-queues = <2>;
845 status-sizes = <64>;
846 queue-sizes = <64 64>;
847 big-endian;
850 rcpm: power-controller@1ee2140 {
851 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
853 #fsl,rcpm-wakeup-cells = <1>;
857 compatible = "fsl,ls1046a-ftm-alarm";
859 fsl,rcpm-wakeup = <&rcpm 0x20000>;
861 big-endian;
865 reserved-memory {
866 #address-cells = <2>;
867 #size-cells = <2>;
870 bman_fbpr: bman-fbpr {
871 compatible = "shared-dma-pool";
874 no-map;
877 qman_fqd: qman-fqd {
878 compatible = "shared-dma-pool";
881 no-map;
884 qman_pfdr: qman-pfdr {
885 compatible = "shared-dma-pool";
888 no-map;
894 compatible = "linaro,optee-tz";
900 #include "qoriq-qman-portals.dtsi"
901 #include "qoriq-bman-portals.dtsi"