Lines Matching +full:nand +full:- +full:bus +full:- +full:width

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
10 /dts-v1/;
12 #include "fsl-ls1046a.dtsi"
16 	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
26 		stdout-path = "serial0:115200n8";
39 	mmc-hs200-1_8v;
40 	sd-uhs-sdr104;
41 	sd-uhs-sdr50;
42 	sd-uhs-sdr25;
43 	sd-uhs-sdr12;
52 		shunt-resistor = <1000>;
55 	temp-sensor@4c {
81 	#address-cells = <2>;
82 	#size-cells = <1>;
83 	/* NAND Flashe and CPLD on board */
88 	nand@0,0 {
89 		compatible = "fsl,ifc-nand";
90 		#address-cells = <1>;
91 		#size-cells = <1>;
95 	cpld: board-control@2,0 {
96 		compatible = "fsl,ls1046ardb-cpld";
105 		compatible = "jedec,spi-nor";
106 		#address-cells = <1>;
107 		#size-cells = <1>;
108 		spi-max-frequency = <50000000>;
109 		spi-rx-bus-width = <4>;
110 		spi-tx-bus-width = <1>;
115 		compatible = "jedec,spi-nor";
116 		#address-cells = <1>;
117 		#size-cells = <1>;
118 		spi-max-frequency = <50000000>;
119 		spi-rx-bus-width = <4>;
120 		spi-tx-bus-width = <1>;
129 #include "fsl-ls1046-post.dtsi"
133 		phy-handle = <&rgmii_phy1>;
134 		phy-connection-type = "rgmii-id";
138 		phy-handle = <&rgmii_phy2>;
139 		phy-connection-type = "rgmii-id";
143 		phy-handle = <&sgmii_phy1>;
144 		phy-connection-type = "sgmii";
148 		phy-handle = <&sgmii_phy2>;
149 		phy-connection-type = "sgmii";
153 		phy-handle = <&aqr106_phy>;
154 		phy-connection-type = "xgmii";
158 		fixed-link = <0 1 1000 0 0>;
159 		phy-connection-type = "xgmii";
163 		rgmii_phy1: ethernet-phy@1 {
167 		rgmii_phy2: ethernet-phy@2 {
171 		sgmii_phy1: ethernet-phy@3 {
175 		sgmii_phy2: ethernet-phy@4 {
181 		aqr106_phy: ethernet-phy@0 {
182 			compatible = "ethernet-phy-ieee802.3-c45";