Lines Matching +full:0 +full:xf08
35 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0>;
47 clocks = <&clockgen 1 0>;
56 reg = <0x1>;
57 clocks = <&clockgen 1 0>;
66 reg = <0x2>;
67 clocks = <&clockgen 1 0>;
76 reg = <0x3>;
77 clocks = <&clockgen 1 0>;
98 arm,psci-suspend-param = <0x0>;
107 reg = <0x0 0x80000000 0 0x80000000>;
118 size = <0 0x1000000>;
119 alignment = <0 0x1000000>;
125 size = <0 0x400000>;
126 alignment = <0 0x400000>;
132 size = <0 0x2000000>;
133 alignment = <0 0x2000000>;
140 #clock-cells = <0>;
148 offset = <0xb0>;
149 mask = <0x02>;
156 thermal-sensors = <&tmu 0>;
267 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
268 <1 14 0xf08>, /* Physical Non-Secure PPI */
269 <1 11 0xf08>, /* Virtual PPI */
270 <1 10 0xf08>; /* Hypervisor PPI */
276 interrupts = <0 106 0x4>,
277 <0 107 0x4>,
278 <0 95 0x4>,
279 <0 97 0x4>;
290 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
291 <0x0 0x1402000 0 0x2000>, /* GICC */
292 <0x0 0x1404000 0 0x2000>, /* GICH */
293 <0x0 0x1406000 0 0x2000>; /* GICV */
294 interrupts = <1 9 0xf08>;
305 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 reg = <0x0 0x1570000 0x0 0x10000>;
317 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
318 "fsl,sec-v4.0";
322 ranges = <0x0 0x00 0x1700000 0x100000>;
323 reg = <0x00 0x1700000 0x0 0x100000>;
324 interrupts = <0 75 0x4>;
328 "fsl,sec-v5.0-job-ring",
329 "fsl,sec-v4.0-job-ring";
330 reg = <0x10000 0x10000>;
331 interrupts = <0 71 0x4>;
336 "fsl,sec-v5.0-job-ring",
337 "fsl,sec-v4.0-job-ring";
338 reg = <0x20000 0x10000>;
339 interrupts = <0 72 0x4>;
344 "fsl,sec-v5.0-job-ring",
345 "fsl,sec-v4.0-job-ring";
346 reg = <0x30000 0x10000>;
347 interrupts = <0 73 0x4>;
352 "fsl,sec-v5.0-job-ring",
353 "fsl,sec-v4.0-job-ring";
354 reg = <0x40000 0x10000>;
355 interrupts = <0 74 0x4>;
361 reg = <0x0 0x1ee0000 0x0 0x10000>;
367 reg = <0x0 0x1530000 0x0 0x10000>;
368 interrupts = <0 43 0x4>;
374 #size-cells = <0>;
375 reg = <0x0 0x1550000 0x0 0x10000>,
376 <0x0 0x40000000 0x0 0x4000000>;
378 interrupts = <0 99 0x4>;
380 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
386 reg = <0x0 0x1560000 0x0 0x10000>;
387 interrupts = <0 62 0x4>;
388 clock-frequency = <0>;
397 reg = <0x0 0x1080000 0x0 0x1000>;
398 interrupts = <0 144 0x4>;
404 reg = <0x0 0x1f00000 0x0 0x10000>;
405 interrupts = <0 33 0x4>;
406 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
407 fsl,tmu-calibration = <0x00000000 0x00000026
408 0x00000001 0x0000002d
409 0x00000002 0x00000032
410 0x00000003 0x00000039
411 0x00000004 0x0000003f
412 0x00000005 0x00000046
413 0x00000006 0x0000004d
414 0x00000007 0x00000054
415 0x00000008 0x0000005a
416 0x00000009 0x00000061
417 0x0000000a 0x0000006a
418 0x0000000b 0x00000071
420 0x00010000 0x00000025
421 0x00010001 0x0000002c
422 0x00010002 0x00000035
423 0x00010003 0x0000003d
424 0x00010004 0x00000045
425 0x00010005 0x0000004e
426 0x00010006 0x00000057
427 0x00010007 0x00000061
428 0x00010008 0x0000006b
429 0x00010009 0x00000076
431 0x00020000 0x00000029
432 0x00020001 0x00000033
433 0x00020002 0x0000003d
434 0x00020003 0x00000049
435 0x00020004 0x00000056
436 0x00020005 0x00000061
437 0x00020006 0x0000006d
439 0x00030000 0x00000021
440 0x00030001 0x0000002a
441 0x00030002 0x0000003c
442 0x00030003 0x0000004e>;
448 reg = <0x0 0x1880000 0x0 0x10000>;
455 reg = <0x0 0x1890000 0x0 0x10000>;
461 ranges = <0x0 0x5 0x08000000 0x8000000>;
465 ranges = <0x0 0x5 0x00000000 0x8000000>;
469 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
471 #size-cells = <0>;
472 reg = <0x0 0x2100000 0x0 0x10000>;
473 interrupts = <0 64 0x4>;
475 clocks = <&clockgen 4 0>;
482 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
484 #size-cells = <0>;
485 reg = <0x0 0x2110000 0x0 0x10000>;
486 interrupts = <0 65 0x4>;
488 clocks = <&clockgen 4 0>;
497 #size-cells = <0>;
498 reg = <0x0 0x2180000 0x0 0x10000>;
499 interrupts = <0 56 0x4>;
501 clocks = <&clockgen 4 0>;
511 #size-cells = <0>;
512 reg = <0x0 0x2190000 0x0 0x10000>;
513 interrupts = <0 57 0x4>;
515 clocks = <&clockgen 4 0>;
522 #size-cells = <0>;
523 reg = <0x0 0x21a0000 0x0 0x10000>;
524 interrupts = <0 58 0x4>;
526 clocks = <&clockgen 4 0>;
533 #size-cells = <0>;
534 reg = <0x0 0x21b0000 0x0 0x10000>;
535 interrupts = <0 59 0x4>;
537 clocks = <&clockgen 4 0>;
543 reg = <0x00 0x21c0500 0x0 0x100>;
544 interrupts = <0 54 0x4>;
545 clocks = <&clockgen 4 0>;
550 reg = <0x00 0x21c0600 0x0 0x100>;
551 interrupts = <0 54 0x4>;
552 clocks = <&clockgen 4 0>;
557 reg = <0x0 0x21d0500 0x0 0x100>;
558 interrupts = <0 55 0x4>;
559 clocks = <&clockgen 4 0>;
564 reg = <0x0 0x21d0600 0x0 0x100>;
565 interrupts = <0 55 0x4>;
566 clocks = <&clockgen 4 0>;
571 reg = <0x0 0x2300000 0x0 0x10000>;
572 interrupts = <0 66 0x4>;
581 reg = <0x0 0x2310000 0x0 0x10000>;
582 interrupts = <0 67 0x4>;
591 reg = <0x0 0x2320000 0x0 0x10000>;
592 interrupts = <0 68 0x4>;
601 reg = <0x0 0x2330000 0x0 0x10000>;
602 interrupts = <0 134 0x4>;
613 ranges = <0x0 0x0 0x2400000 0x40000>;
614 reg = <0x0 0x2400000 0x0 0x480>;
622 reg = <0x80 0x80>;
623 #address-cells = <0>;
632 #size-cells = <0>;
635 reg = <0x700 0x80>;
643 reg = <0x1000 0x800>;
648 reg = <0x2000 0x200>;
655 reg = <0x2200 0x200>;
664 ranges = <0x0 0x10000 0x6000>;
666 data-only@0 {
669 reg = <0x0 0x6000>;
676 reg = <0x0 0x2950000 0x0 0x1000>;
677 interrupts = <0 48 0x4>;
678 clocks = <&clockgen 0 0>;
685 reg = <0x0 0x2960000 0x0 0x1000>;
686 interrupts = <0 49 0x4>;
687 clocks = <&clockgen 4 0>;
694 reg = <0x0 0x2970000 0x0 0x1000>;
695 interrupts = <0 50 0x4>;
696 clocks = <&clockgen 4 0>;
703 reg = <0x0 0x2980000 0x0 0x1000>;
704 interrupts = <0 51 0x4>;
705 clocks = <&clockgen 4 0>;
712 reg = <0x0 0x2990000 0x0 0x1000>;
713 interrupts = <0 52 0x4>;
714 clocks = <&clockgen 4 0>;
721 reg = <0x0 0x29a0000 0x0 0x1000>;
722 interrupts = <0 53 0x4>;
723 clocks = <&clockgen 4 0>;
730 reg = <0x0 0x2ad0000 0x0 0x10000>;
731 interrupts = <0 83 0x4>;
732 clocks = <&clockgen 4 0>;
740 reg = <0x0 0x2c00000 0x0 0x10000>,
741 <0x0 0x2c10000 0x0 0x10000>,
742 <0x0 0x2c20000 0x0 0x10000>;
743 interrupts = <0 103 0x4>,
744 <0 103 0x4>;
749 clocks = <&clockgen 4 0>,
750 <&clockgen 4 0>;
755 reg = <0x0 0x2f00000 0x0 0x10000>;
756 interrupts = <0 60 0x4>;
758 snps,quirk-frame-length-adjustment = <0x20>;
766 reg = <0x0 0x3000000 0x0 0x10000>;
767 interrupts = <0 61 0x4>;
769 snps,quirk-frame-length-adjustment = <0x20>;
777 reg = <0x0 0x3100000 0x0 0x10000>;
778 interrupts = <0 63 0x4>;
780 snps,quirk-frame-length-adjustment = <0x20>;
788 reg = <0x0 0x3200000 0x0 0x10000>,
789 <0x0 0x20140520 0x0 0x4>;
791 interrupts = <0 69 0x4>;
792 clocks = <&clockgen 4 0>;
798 reg = <0x0 0x1571000 0x0 0x8>;
800 interrupts = <0 116 0x4>;
805 reg = <0x0 0x1572000 0x0 0x8>;
807 interrupts = <0 126 0x4>;
812 reg = <0x0 0x1573000 0x0 0x8>;
814 interrupts = <0 160 0x4>;
819 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
820 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
822 interrupts = <0 118 0x4>, /* controller interrupt */
823 <0 117 0x4>; /* PME interrupt */
830 bus-range = <0x0 0xff>;
831 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
832 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
835 interrupt-map-mask = <0 0 0 7>;
836 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
837 <0000 0 0 2 &gic 0 111 0x4>,
838 <0000 0 0 3 &gic 0 112 0x4>,
839 <0000 0 0 4 &gic 0 113 0x4>;
845 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
846 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
848 interrupts = <0 128 0x4>,
849 <0 127 0x4>;
856 bus-range = <0x0 0xff>;
857 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
858 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
861 interrupt-map-mask = <0 0 0 7>;
862 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
863 <0000 0 0 2 &gic 0 121 0x4>,
864 <0000 0 0 3 &gic 0 122 0x4>,
865 <0000 0 0 4 &gic 0 123 0x4>;
871 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
872 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
874 interrupts = <0 162 0x4>,
875 <0 161 0x4>;
882 bus-range = <0x0 0xff>;
883 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
884 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
887 interrupt-map-mask = <0 0 0 7>;
888 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
889 <0000 0 0 2 &gic 0 155 0x4>,
890 <0000 0 0 3 &gic 0 156 0x4>,
891 <0000 0 0 4 &gic 0 157 0x4>;
897 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
898 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
899 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
909 block-offset = <0x10000>;
918 reg = <0x0 0x1ee2140 0x0 0x4>;
924 reg = <0x0 0x29d0000 0x0 0x10000>;
925 fsl,rcpm-wakeup = <&rcpm 0x20000>;