Lines Matching +full:cpu +full:- +full:idle +full:- +full:states
4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
36 #size-cells = <0>;
38 cpu-map {
41 cpu = <&A57_0>;
44 cpu = <&A57_1>;
50 cpu = <&A53_0>;
53 cpu = <&A53_1>;
56 cpu = <&A53_2>;
59 cpu = <&A53_3>;
64 idle-states {
65 entry-method = "psci";
67 CPU_SLEEP_0: cpu-sleep-0 {
68 compatible = "arm,idle-state";
69 arm,psci-suspend-param = <0x0010000>;
70 local-timer-stop;
71 entry-latency-us = <300>;
72 exit-latency-us = <1200>;
73 min-residency-us = <2000>;
76 CLUSTER_SLEEP_0: cluster-sleep-0 {
77 compatible = "arm,idle-state";
78 arm,psci-suspend-param = <0x1010000>;
79 local-timer-stop;
80 entry-latency-us = <400>;
81 exit-latency-us = <1200>;
82 min-residency-us = <2500>;
86 A57_0: cpu@0 {
87 compatible = "arm,cortex-a57";
89 device_type = "cpu";
90 enable-method = "psci";
91 i-cache-size = <0xc000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <256>;
97 next-level-cache = <&A57_L2>;
99 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
100 capacity-dmips-mhz = <1024>;
101 dynamic-power-coefficient = <530>;
104 A57_1: cpu@1 {
105 compatible = "arm,cortex-a57";
107 device_type = "cpu";
108 enable-method = "psci";
109 i-cache-size = <0xc000>;
110 i-cache-line-size = <64>;
111 i-cache-sets = <256>;
112 d-cache-size = <0x8000>;
113 d-cache-line-size = <64>;
114 d-cache-sets = <256>;
115 next-level-cache = <&A57_L2>;
117 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
118 capacity-dmips-mhz = <1024>;
119 dynamic-power-coefficient = <530>;
122 A53_0: cpu@100 {
123 compatible = "arm,cortex-a53";
125 device_type = "cpu";
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
135 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
136 capacity-dmips-mhz = <578>;
137 dynamic-power-coefficient = <140>;
140 A53_1: cpu@101 {
141 compatible = "arm,cortex-a53";
143 device_type = "cpu";
144 enable-method = "psci";
145 i-cache-size = <0x8000>;
146 i-cache-line-size = <64>;
147 i-cache-sets = <256>;
148 d-cache-size = <0x8000>;
149 d-cache-line-size = <64>;
150 d-cache-sets = <128>;
151 next-level-cache = <&A53_L2>;
153 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
154 capacity-dmips-mhz = <578>;
155 dynamic-power-coefficient = <140>;
158 A53_2: cpu@102 {
159 compatible = "arm,cortex-a53";
161 device_type = "cpu";
162 enable-method = "psci";
163 i-cache-size = <0x8000>;
164 i-cache-line-size = <64>;
165 i-cache-sets = <256>;
166 d-cache-size = <0x8000>;
167 d-cache-line-size = <64>;
168 d-cache-sets = <128>;
169 next-level-cache = <&A53_L2>;
171 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
172 capacity-dmips-mhz = <578>;
173 dynamic-power-coefficient = <140>;
176 A53_3: cpu@103 {
177 compatible = "arm,cortex-a53";
179 device_type = "cpu";
180 enable-method = "psci";
181 i-cache-size = <0x8000>;
182 i-cache-line-size = <64>;
183 i-cache-sets = <256>;
184 d-cache-size = <0x8000>;
185 d-cache-line-size = <64>;
186 d-cache-sets = <128>;
187 next-level-cache = <&A53_L2>;
189 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
190 capacity-dmips-mhz = <578>;
191 dynamic-power-coefficient = <140>;
194 A57_L2: l2-cache0 {
196 cache-size = <0x200000>;
197 cache-line-size = <64>;
198 cache-sets = <2048>;
201 A53_L2: l2-cache1 {
203 cache-size = <0x100000>;
204 cache-line-size = <64>;
205 cache-sets = <1024>;
209 pmu-a57 {
210 compatible = "arm,cortex-a57-pmu";
213 interrupt-affinity = <&A57_0>,
217 pmu-a53 {
218 compatible = "arm,cortex-a53-pmu";
223 interrupt-affinity = <&A53_0>,
231 cpu = <&A57_0>;
235 cpu = <&A57_1>;
239 cpu = <&A53_0>;
243 cpu = <&A53_1>;
247 cpu = <&A53_2>;
251 cpu = <&A53_3>;
255 remote-endpoint = <&replicator_in_port0>;
259 remote-endpoint = <&etf0_out_port>;
263 remote-endpoint = <&main_funnel_in_port2>;
270 remote-endpoint = <&stm_out_port>;
276 cpu = <&A57_0>;
280 cpu = <&A57_1>;
284 cpu = <&A53_0>;
288 cpu = <&A53_1>;
292 cpu = <&A53_2>;
296 cpu = <&A53_3>;