Lines Matching +full:rng +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
30 enable-method = "spin-table";
31 cpu-release-addr = <0x1 0x0000fff8>;
32 next-level-cache = <&xgene_L2_0>;
38 enable-method = "spin-table";
39 cpu-release-addr = <0x1 0x0000fff8>;
40 next-level-cache = <&xgene_L2_1>;
46 enable-method = "spin-table";
47 cpu-release-addr = <0x1 0x0000fff8>;
48 next-level-cache = <&xgene_L2_1>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
56 next-level-cache = <&xgene_L2_2>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
70 enable-method = "spin-table";
71 cpu-release-addr = <0x1 0x0000fff8>;
72 next-level-cache = <&xgene_L2_3>;
78 enable-method = "spin-table";
79 cpu-release-addr = <0x1 0x0000fff8>;
80 next-level-cache = <&xgene_L2_3>;
82 xgene_L2_0: l2-cache-0 {
85 xgene_L2_1: l2-cache-1 {
88 xgene_L2_2: l2-cache-2 {
91 xgene_L2_3: l2-cache-3 {
96 gic: interrupt-controller@78010000 {
97 compatible = "arm,cortex-a15-gic";
98 #interrupt-cells = <3>;
99 interrupt-controller;
108 compatible = "arm,armv8-timer";
110 <1 13 0xff08>, /* Non-secure Phys IRQ */
113 clock-frequency = <50000000>;
117 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
122 compatible = "simple-bus";
123 #address-cells = <2>;
124 #size-cells = <2>;
126 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
129 #address-cells = <2>;
130 #size-cells = <2>;
133 compatible = "fixed-clock";
134 #clock-cells = <1>;
135 clock-frequency = <100000000>;
136 clock-output-names = "refclk";
140 compatible = "apm,xgene-pcppll-clock";
141 #clock-cells = <1>;
143 clock-names = "pcppll";
145 clock-output-names = "pcppll";
150 compatible = "apm,xgene-socpll-clock";
151 #clock-cells = <1>;
153 clock-names = "socpll";
155 clock-output-names = "socpll";
160 compatible = "fixed-factor-clock";
161 #clock-cells = <1>;
163 clock-names = "socplldiv2";
164 clock-mult = <1>;
165 clock-div = <2>;
166 clock-output-names = "socplldiv2";
170 compatible = "apm,xgene-device-clock";
171 #clock-cells = <1>;
174 reg-names = "div-reg";
175 divider-offset = <0x164>;
176 divider-width = <0x5>;
177 divider-shift = <0x0>;
178 clock-output-names = "ahbclk";
182 compatible = "apm,xgene-device-clock";
183 #clock-cells = <1>;
187 reg-names = "csr-reg", "div-reg";
188 csr-offset = <0x0>;
189 csr-mask = <0x2>;
190 enable-offset = <0x8>;
191 enable-mask = <0x2>;
192 divider-offset = <0x178>;
193 divider-width = <0x8>;
194 divider-shift = <0x0>;
195 clock-output-names = "sdioclk";
199 compatible = "apm,xgene-device-clock";
200 #clock-cells = <1>;
202 clock-names = "ethclk";
204 reg-names = "div-reg";
205 divider-offset = <0x238>;
206 divider-width = <0x9>;
207 divider-shift = <0x0>;
208 clock-output-names = "ethclk";
212 compatible = "apm,xgene-device-clock";
213 #clock-cells = <1>;
216 reg-names = "csr-reg";
217 clock-output-names = "menetclk";
221 compatible = "apm,xgene-device-clock";
222 #clock-cells = <1>;
225 reg-names = "csr-reg";
226 csr-mask = <0xa>;
227 enable-mask = <0xf>;
228 clock-output-names = "sge0clk";
232 compatible = "apm,xgene-device-clock";
233 #clock-cells = <1>;
236 reg-names = "csr-reg";
237 csr-mask = <0x3>;
238 clock-output-names = "xge0clk";
242 compatible = "apm,xgene-device-clock";
244 #clock-cells = <1>;
247 reg-names = "csr-reg";
248 csr-mask = <0x3>;
249 clock-output-names = "xge1clk";
253 compatible = "apm,xgene-device-clock";
254 #clock-cells = <1>;
257 reg-names = "csr-reg";
258 clock-output-names = "sataphy1clk";
260 csr-offset = <0x4>;
261 csr-mask = <0x00>;
262 enable-offset = <0x0>;
263 enable-mask = <0x06>;
267 compatible = "apm,xgene-device-clock";
268 #clock-cells = <1>;
271 reg-names = "csr-reg";
272 clock-output-names = "sataphy2clk";
274 csr-offset = <0x4>;
275 csr-mask = <0x3a>;
276 enable-offset = <0x0>;
277 enable-mask = <0x06>;
281 compatible = "apm,xgene-device-clock";
282 #clock-cells = <1>;
285 reg-names = "csr-reg";
286 clock-output-names = "sataphy3clk";
288 csr-offset = <0x4>;
289 csr-mask = <0x3a>;
290 enable-offset = <0x0>;
291 enable-mask = <0x06>;
295 compatible = "apm,xgene-device-clock";
296 #clock-cells = <1>;
299 reg-names = "csr-reg";
300 clock-output-names = "sata01clk";
301 csr-offset = <0x4>;
302 csr-mask = <0x05>;
303 enable-offset = <0x0>;
304 enable-mask = <0x39>;
308 compatible = "apm,xgene-device-clock";
309 #clock-cells = <1>;
312 reg-names = "csr-reg";
313 clock-output-names = "sata23clk";
314 csr-offset = <0x4>;
315 csr-mask = <0x05>;
316 enable-offset = <0x0>;
317 enable-mask = <0x39>;
321 compatible = "apm,xgene-device-clock";
322 #clock-cells = <1>;
325 reg-names = "csr-reg";
326 clock-output-names = "sata45clk";
327 csr-offset = <0x4>;
328 csr-mask = <0x05>;
329 enable-offset = <0x0>;
330 enable-mask = <0x39>;
334 compatible = "apm,xgene-device-clock";
335 #clock-cells = <1>;
338 reg-names = "csr-reg";
339 csr-offset = <0xc>;
340 csr-mask = <0x2>;
341 enable-offset = <0x10>;
342 enable-mask = <0x2>;
343 clock-output-names = "rtcclk";
347 compatible = "apm,xgene-device-clock";
348 #clock-cells = <1>;
351 reg-names = "csr-reg";
352 csr-offset = <0xc>;
353 csr-mask = <0x10>;
354 enable-offset = <0x10>;
355 enable-mask = <0x10>;
356 clock-output-names = "rngpkaclk";
361 compatible = "apm,xgene-device-clock";
362 #clock-cells = <1>;
365 reg-names = "csr-reg";
366 clock-output-names = "pcie0clk";
371 compatible = "apm,xgene-device-clock";
372 #clock-cells = <1>;
375 reg-names = "csr-reg";
376 clock-output-names = "pcie1clk";
381 compatible = "apm,xgene-device-clock";
382 #clock-cells = <1>;
385 reg-names = "csr-reg";
386 clock-output-names = "pcie2clk";
391 compatible = "apm,xgene-device-clock";
392 #clock-cells = <1>;
395 reg-names = "csr-reg";
396 clock-output-names = "pcie3clk";
401 compatible = "apm,xgene-device-clock";
402 #clock-cells = <1>;
405 reg-names = "csr-reg";
406 clock-output-names = "pcie4clk";
410 compatible = "apm,xgene-device-clock";
411 #clock-cells = <1>;
414 reg-names = "csr-reg";
415 clock-output-names = "dmaclk";
420 compatible = "apm,xgene1-msi";
421 msi-controller;
441 scu: system-clk-controller@17000000 {
442 compatible = "apm,xgene-scu","syscon";
447 compatible = "syscon-reboot";
454 compatible = "apm,xgene-csw", "syscon";
459 compatible = "apm,xgene-mcb", "syscon";
464 compatible = "apm,xgene-mcb", "syscon";
469 compatible = "apm,xgene-efuse", "syscon";
474 compatible = "apm,xgene-rb", "syscon";
479 compatible = "apm,xgene-edac";
480 #address-cells = <2>;
481 #size-cells = <2>;
483 regmap-csw = <&csw>;
484 regmap-mcba = <&mcba>;
485 regmap-mcbb = <&mcbb>;
486 regmap-efuse = <&efuse>;
487 regmap-rb = <&rb>;
494 compatible = "apm,xgene-edac-mc";
496 memory-controller = <0>;
500 compatible = "apm,xgene-edac-mc";
502 memory-controller = <1>;
506 compatible = "apm,xgene-edac-mc";
508 memory-controller = <2>;
512 compatible = "apm,xgene-edac-mc";
514 memory-controller = <3>;
518 compatible = "apm,xgene-edac-pmd";
520 pmd-controller = <0>;
524 compatible = "apm,xgene-edac-pmd";
526 pmd-controller = <1>;
530 compatible = "apm,xgene-edac-pmd";
532 pmd-controller = <2>;
536 compatible = "apm,xgene-edac-pmd";
538 pmd-controller = <3>;
542 compatible = "apm,xgene-edac-l3";
547 compatible = "apm,xgene-edac-soc-v1";
553 compatible = "apm,xgene-pmu-v2";
554 #address-cells = <2>;
555 #size-cells = <2>;
557 regmap-csw = <&csw>;
558 regmap-mcba = <&mcba>;
559 regmap-mcbb = <&mcbb>;
564 compatible = "apm,xgene-pmu-l3c";
569 compatible = "apm,xgene-pmu-iob";
574 compatible = "apm,xgene-pmu-mcb";
576 enable-bit-index = <0>;
580 compatible = "apm,xgene-pmu-mcb";
582 enable-bit-index = <1>;
586 compatible = "apm,xgene-pmu-mc";
588 enable-bit-index = <0>;
592 compatible = "apm,xgene-pmu-mc";
594 enable-bit-index = <1>;
598 compatible = "apm,xgene-pmu-mc";
600 enable-bit-index = <2>;
604 compatible = "apm,xgene-pmu-mc";
606 enable-bit-index = <3>;
613 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
614 #interrupt-cells = <1>;
615 #size-cells = <2>;
616 #address-cells = <3>;
619 reg-names = "csr", "cfg";
623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
625 bus-range = <0x00 0xff>;
626 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
631 dma-coherent;
633 msi-parent = <&msi>;
639 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
640 #interrupt-cells = <1>;
641 #size-cells = <2>;
642 #address-cells = <3>;
645 reg-names = "csr", "cfg";
649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
651 bus-range = <0x00 0xff>;
652 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
657 dma-coherent;
659 msi-parent = <&msi>;
665 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
666 #interrupt-cells = <1>;
667 #size-cells = <2>;
668 #address-cells = <3>;
671 reg-names = "csr", "cfg";
675 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
677 bus-range = <0x00 0xff>;
678 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
679 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
683 dma-coherent;
685 msi-parent = <&msi>;
691 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
692 #interrupt-cells = <1>;
693 #size-cells = <2>;
694 #address-cells = <3>;
697 reg-names = "csr", "cfg";
701 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
703 bus-range = <0x00 0xff>;
704 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
705 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
709 dma-coherent;
711 msi-parent = <&msi>;
717 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
718 #interrupt-cells = <1>;
719 #size-cells = <2>;
720 #address-cells = <3>;
723 reg-names = "csr", "cfg";
727 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
729 bus-range = <0x00 0xff>;
730 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
731 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
735 dma-coherent;
737 msi-parent = <&msi>;
741 compatible = "apm,xgene-slimpro-mbox";
743 #mbox-cells = <1>;
755 compatible = "apm,xgene-slimpro-i2c";
760 compatible = "apm,xgene-slimpro-hwmon";
769 reg-shift = <2>;
770 clock-frequency = <10000000>; /* Updated by bootloader */
771 interrupt-parent = <&gic>;
780 reg-shift = <2>;
781 clock-frequency = <10000000>; /* Updated by bootloader */
782 interrupt-parent = <&gic>;
791 reg-shift = <2>;
792 clock-frequency = <10000000>; /* Updated by bootloader */
793 interrupt-parent = <&gic>;
802 reg-shift = <2>;
803 clock-frequency = <10000000>; /* Updated by bootloader */
804 interrupt-parent = <&gic>;
809 compatible = "arasan,sdhci-4.9a";
812 dma-coherent;
813 no-1-8-v;
814 clock-names = "clk_xin", "clk_ahb";
819 compatible = "apm,xgene-gpio";
821 gpio-controller;
822 #gpio-cells = <2>;
826 compatible = "snps,dw-apb-gpio";
828 #address-cells = <1>;
829 #size-cells = <0>;
831 porta: gpio-controller@0 {
832 compatible = "snps,dw-apb-gpio-port";
833 gpio-controller;
834 #gpio-cells = <2>;
835 snps,nr-gpios = <32>;
842 #address-cells = <1>;
843 #size-cells = <0>;
844 compatible = "snps,designware-i2c";
847 #clock-cells = <1>;
853 compatible = "apm,xgene-phy";
855 #phy-cells = <1>;
858 apm,tx-boost-gain = <30 30 30 30 30 30>;
859 apm,tx-eye-tuning = <2 10 10 2 10 10>;
863 compatible = "apm,xgene-phy";
865 #phy-cells = <1>;
868 apm,tx-boost-gain = <30 30 30 30 30 30>;
869 apm,tx-eye-tuning = <1 10 10 2 10 10>;
873 compatible = "apm,xgene-phy";
875 #phy-cells = <1>;
878 apm,tx-boost-gain = <31 31 31 31 31 31>;
879 apm,tx-eye-tuning = <2 10 10 2 10 10>;
883 compatible = "apm,xgene-ahci";
890 dma-coherent;
894 phy-names = "sata-phy";
898 compatible = "apm,xgene-ahci";
905 dma-coherent;
909 phy-names = "sata-phy";
913 compatible = "apm,xgene-ahci";
919 dma-coherent;
923 phy-names = "sata-phy";
932 dma-coherent;
941 dma-coherent;
946 compatible = "apm,xgene-gpio-sb";
948 #gpio-cells = <2>;
949 gpio-controller;
956 interrupt-parent = <&gic>;
957 #interrupt-cells = <2>;
958 interrupt-controller;
962 compatible = "apm,xgene-rtc";
965 #clock-cells = <1>;
970 compatible = "apm,xgene-mdio-rgmii";
971 #address-cells = <1>;
972 #size-cells = <0>;
978 compatible = "apm,xgene-enet";
983 reg-names = "enet_csr", "ring_csr", "ring_cmd";
985 dma-coherent;
988 local-mac-address = [00 00 00 00 00 00];
989 phy-connection-type = "rgmii";
990 phy-handle = <&menetphy>,<&menet0phy>;
992 compatible = "apm,xgene-mdio";
993 #address-cells = <1>;
994 #size-cells = <0>;
996 compatible = "ethernet-phy-id001c.c915";
1004 compatible = "apm,xgene1-sgenet";
1009 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1012 dma-coherent;
1014 local-mac-address = [00 00 00 00 00 00];
1015 phy-connection-type = "sgmii";
1016 phy-handle = <&sgenet0phy>;
1020 compatible = "apm,xgene1-sgenet";
1025 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1028 port-id = <1>;
1029 dma-coherent;
1030 local-mac-address = [00 00 00 00 00 00];
1031 phy-connection-type = "sgmii";
1032 phy-handle = <&sgenet1phy>;
1036 compatible = "apm,xgene1-xgenet";
1041 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1051 dma-coherent;
1054 local-mac-address = [00 00 00 00 00 00];
1055 phy-connection-type = "xgmii";
1059 compatible = "apm,xgene1-xgenet";
1064 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1067 port-id = <1>;
1068 dma-coherent;
1071 local-mac-address = [00 00 00 00 00 00];
1072 phy-connection-type = "xgmii";
1075 rng: rng@10520000 { label
1076 compatible = "apm,xgene-rng";
1083 compatible = "apm,xgene-storm-dma";
1094 dma-coherent;