Lines Matching +full:0 +full:x1f200000
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
53 reg = <0x0 0x200>;
55 cpu-release-addr = <0x1 0x0000fff8>;
61 reg = <0x0 0x201>;
63 cpu-release-addr = <0x1 0x0000fff8>;
69 reg = <0x0 0x300>;
71 cpu-release-addr = <0x1 0x0000fff8>;
77 reg = <0x0 0x301>;
79 cpu-release-addr = <0x1 0x0000fff8>;
82 xgene_L2_0: l2-cache-0 {
100 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
101 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
102 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
103 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
104 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
109 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
110 <1 13 0xff08>, /* Non-secure Phys IRQ */
111 <1 14 0xff08>, /* Virt IRQ */
112 <1 15 0xff08>; /* Hyp IRQ */
118 interrupts = <1 12 0xff04>;
126 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
142 clocks = <&refclk 0>;
144 reg = <0x0 0x17000100 0x0 0x1000>;
146 type = <0>;
152 clocks = <&refclk 0>;
154 reg = <0x0 0x17000120 0x0 0x1000>;
162 clocks = <&socpll 0>;
172 clocks = <&socplldiv2 0>;
173 reg = <0x0 0x17000000 0x0 0x2000>;
175 divider-offset = <0x164>;
176 divider-width = <0x5>;
177 divider-shift = <0x0>;
184 clocks = <&socplldiv2 0>;
185 reg = <0x0 0x1f2ac000 0x0 0x1000
186 0x0 0x17000000 0x0 0x2000>;
188 csr-offset = <0x0>;
189 csr-mask = <0x2>;
190 enable-offset = <0x8>;
191 enable-mask = <0x2>;
192 divider-offset = <0x178>;
193 divider-width = <0x8>;
194 divider-shift = <0x0>;
201 clocks = <&socplldiv2 0>;
203 reg = <0x0 0x17000000 0x0 0x1000>;
205 divider-offset = <0x238>;
206 divider-width = <0x9>;
207 divider-shift = <0x0>;
214 clocks = <ðclk 0>;
215 reg = <0x0 0x1702c000 0x0 0x1000>;
223 clocks = <&socplldiv2 0>;
224 reg = <0x0 0x1f21c000 0x0 0x1000>;
226 csr-mask = <0xa>;
227 enable-mask = <0xf>;
234 clocks = <&socplldiv2 0>;
235 reg = <0x0 0x1f61c000 0x0 0x1000>;
237 csr-mask = <0x3>;
245 clocks = <&socplldiv2 0>;
246 reg = <0x0 0x1f62c000 0x0 0x1000>;
248 csr-mask = <0x3>;
255 clocks = <&socplldiv2 0>;
256 reg = <0x0 0x1f21c000 0x0 0x1000>;
260 csr-offset = <0x4>;
261 csr-mask = <0x00>;
262 enable-offset = <0x0>;
263 enable-mask = <0x06>;
269 clocks = <&socplldiv2 0>;
270 reg = <0x0 0x1f22c000 0x0 0x1000>;
274 csr-offset = <0x4>;
275 csr-mask = <0x3a>;
276 enable-offset = <0x0>;
277 enable-mask = <0x06>;
283 clocks = <&socplldiv2 0>;
284 reg = <0x0 0x1f23c000 0x0 0x1000>;
288 csr-offset = <0x4>;
289 csr-mask = <0x3a>;
290 enable-offset = <0x0>;
291 enable-mask = <0x06>;
297 clocks = <&socplldiv2 0>;
298 reg = <0x0 0x1f21c000 0x0 0x1000>;
301 csr-offset = <0x4>;
302 csr-mask = <0x05>;
303 enable-offset = <0x0>;
304 enable-mask = <0x39>;
310 clocks = <&socplldiv2 0>;
311 reg = <0x0 0x1f22c000 0x0 0x1000>;
314 csr-offset = <0x4>;
315 csr-mask = <0x05>;
316 enable-offset = <0x0>;
317 enable-mask = <0x39>;
323 clocks = <&socplldiv2 0>;
324 reg = <0x0 0x1f23c000 0x0 0x1000>;
327 csr-offset = <0x4>;
328 csr-mask = <0x05>;
329 enable-offset = <0x0>;
330 enable-mask = <0x39>;
336 clocks = <&socplldiv2 0>;
337 reg = <0x0 0x17000000 0x0 0x2000>;
339 csr-offset = <0xc>;
340 csr-mask = <0x2>;
341 enable-offset = <0x10>;
342 enable-mask = <0x2>;
349 clocks = <&socplldiv2 0>;
350 reg = <0x0 0x17000000 0x0 0x2000>;
352 csr-offset = <0xc>;
353 csr-mask = <0x10>;
354 enable-offset = <0x10>;
355 enable-mask = <0x10>;
363 clocks = <&socplldiv2 0>;
364 reg = <0x0 0x1f2bc000 0x0 0x1000>;
373 clocks = <&socplldiv2 0>;
374 reg = <0x0 0x1f2cc000 0x0 0x1000>;
383 clocks = <&socplldiv2 0>;
384 reg = <0x0 0x1f2dc000 0x0 0x1000>;
393 clocks = <&socplldiv2 0>;
394 reg = <0x0 0x1f50c000 0x0 0x1000>;
403 clocks = <&socplldiv2 0>;
404 reg = <0x0 0x1f51c000 0x0 0x1000>;
412 clocks = <&socplldiv2 0>;
413 reg = <0x0 0x1f27c000 0x0 0x1000>;
422 reg = <0x00 0x79000000 0x0 0x900000>;
423 interrupts = < 0x0 0x10 0x4
424 0x0 0x11 0x4
425 0x0 0x12 0x4
426 0x0 0x13 0x4
427 0x0 0x14 0x4
428 0x0 0x15 0x4
429 0x0 0x16 0x4
430 0x0 0x17 0x4
431 0x0 0x18 0x4
432 0x0 0x19 0x4
433 0x0 0x1a 0x4
434 0x0 0x1b 0x4
435 0x0 0x1c 0x4
436 0x0 0x1d 0x4
437 0x0 0x1e 0x4
438 0x0 0x1f 0x4>;
443 reg = <0x0 0x17000000 0x0 0x400>;
449 offset = <0x14>;
450 mask = <0x1>;
455 reg = <0x0 0x7e200000 0x0 0x1000>;
460 reg = <0x0 0x7e700000 0x0 0x1000>;
465 reg = <0x0 0x7e720000 0x0 0x1000>;
470 reg = <0x0 0x1054a000 0x0 0x20>;
475 reg = <0x0 0x7e000000 0x0 0x10>;
488 reg = <0x0 0x78800000 0x0 0x100>;
489 interrupts = <0x0 0x20 0x4>,
490 <0x0 0x21 0x4>,
491 <0x0 0x27 0x4>;
495 reg = <0x0 0x7e800000 0x0 0x1000>;
496 memory-controller = <0>;
501 reg = <0x0 0x7e840000 0x0 0x1000>;
507 reg = <0x0 0x7e880000 0x0 0x1000>;
513 reg = <0x0 0x7e8c0000 0x0 0x1000>;
519 reg = <0x0 0x7c000000 0x0 0x200000>;
520 pmd-controller = <0>;
525 reg = <0x0 0x7c200000 0x0 0x200000>;
531 reg = <0x0 0x7c400000 0x0 0x200000>;
537 reg = <0x0 0x7c600000 0x0 0x200000>;
543 reg = <0x0 0x7e600000 0x0 0x1000>;
548 reg = <0x0 0x7e930000 0x0 0x1000>;
560 reg = <0x0 0x78810000 0x0 0x1000>;
561 interrupts = <0x0 0x22 0x4>;
565 reg = <0x0 0x7e610000 0x0 0x1000>;
570 reg = <0x0 0x7e940000 0x0 0x1000>;
575 reg = <0x0 0x7e710000 0x0 0x1000>;
576 enable-bit-index = <0>;
581 reg = <0x0 0x7e730000 0x0 0x1000>;
587 reg = <0x0 0x7e810000 0x0 0x1000>;
588 enable-bit-index = <0>;
593 reg = <0x0 0x7e850000 0x0 0x1000>;
599 reg = <0x0 0x7e890000 0x0 0x1000>;
605 reg = <0x0 0x7e8d0000 0x0 0x1000>;
617 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
618 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
620 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
621 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
622 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
624 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
625 bus-range = <0x00 0xff>;
626 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
628 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
629 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
630 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
632 clocks = <&pcie0clk 0>;
643 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
644 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
646 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
647 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
648 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
650 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
651 bus-range = <0x00 0xff>;
652 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
654 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
655 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
656 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
658 clocks = <&pcie1clk 0>;
669 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
670 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
672 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
673 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
674 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
675 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
676 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
677 bus-range = <0x00 0xff>;
678 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
679 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
680 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
681 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
682 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
684 clocks = <&pcie2clk 0>;
695 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
696 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
698 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
699 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
700 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
701 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
702 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
703 bus-range = <0x00 0xff>;
704 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
705 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
706 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
707 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
708 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
710 clocks = <&pcie3clk 0>;
721 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
722 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
724 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
725 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
726 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
727 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
728 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
729 bus-range = <0x00 0xff>;
730 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
731 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
732 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
733 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
734 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
736 clocks = <&pcie4clk 0>;
742 reg = <0x0 0x10540000 0x0 0xa000>;
744 interrupts = <0x0 0x0 0x4>,
745 <0x0 0x1 0x4>,
746 <0x0 0x2 0x4>,
747 <0x0 0x3 0x4>,
748 <0x0 0x4 0x4>,
749 <0x0 0x5 0x4>,
750 <0x0 0x6 0x4>,
751 <0x0 0x7 0x4>;
756 mboxes = <&mailbox 0>;
768 reg = <0 0x1c020000 0x0 0x1000>;
772 interrupts = <0x0 0x4c 0x4>;
779 reg = <0 0x1c021000 0x0 0x1000>;
783 interrupts = <0x0 0x4d 0x4>;
790 reg = <0 0x1c022000 0x0 0x1000>;
794 interrupts = <0x0 0x4e 0x4>;
801 reg = <0 0x1c023000 0x0 0x1000>;
805 interrupts = <0x0 0x4f 0x4>;
810 reg = <0x0 0x1c000000 0x0 0x100>;
811 interrupts = <0x0 0x49 0x4>;
815 clocks = <&sdioclk 0>, <&ahbclk 0>;
820 reg = <0x0 0x1701c000 0x0 0x40>;
827 reg = <0x0 0x1c024000 0x0 0x1000>;
829 #size-cells = <0>;
831 porta: gpio-controller@0 {
836 reg = <0>;
843 #size-cells = <0>;
845 reg = <0x0 0x10512000 0x0 0x1000>;
846 interrupts = <0 0x44 0x4>;
848 clocks = <&ahbclk 0>;
849 bus_num = <0>;
854 reg = <0x0 0x1f21a000 0x0 0x100>;
856 clocks = <&sataphy1clk 0>;
864 reg = <0x0 0x1f22a000 0x0 0x100>;
866 clocks = <&sataphy2clk 0>;
874 reg = <0x0 0x1f23a000 0x0 0x100>;
876 clocks = <&sataphy3clk 0>;
884 reg = <0x0 0x1a000000 0x0 0x1000>,
885 <0x0 0x1f210000 0x0 0x1000>,
886 <0x0 0x1f21d000 0x0 0x1000>,
887 <0x0 0x1f21e000 0x0 0x1000>,
888 <0x0 0x1f217000 0x0 0x1000>;
889 interrupts = <0x0 0x86 0x4>;
892 clocks = <&sata01clk 0>;
893 phys = <&phy1 0>;
899 reg = <0x0 0x1a400000 0x0 0x1000>,
900 <0x0 0x1f220000 0x0 0x1000>,
901 <0x0 0x1f22d000 0x0 0x1000>,
902 <0x0 0x1f22e000 0x0 0x1000>,
903 <0x0 0x1f227000 0x0 0x1000>;
904 interrupts = <0x0 0x87 0x4>;
907 clocks = <&sata23clk 0>;
908 phys = <&phy2 0>;
914 reg = <0x0 0x1a800000 0x0 0x1000>,
915 <0x0 0x1f230000 0x0 0x1000>,
916 <0x0 0x1f23d000 0x0 0x1000>,
917 <0x0 0x1f23e000 0x0 0x1000>;
918 interrupts = <0x0 0x88 0x4>;
921 clocks = <&sata45clk 0>;
922 phys = <&phy3 0>;
930 reg = <0x0 0x19000000 0x0 0x100000>;
931 interrupts = <0x0 0x89 0x4>;
939 reg = <0x0 0x19800000 0x0 0x100000>;
940 interrupts = <0x0 0x8a 0x4>;
947 reg = <0x0 0x17001000 0x0 0x400>;
950 interrupts = <0x0 0x28 0x1>,
951 <0x0 0x29 0x1>,
952 <0x0 0x2a 0x1>,
953 <0x0 0x2b 0x1>,
954 <0x0 0x2c 0x1>,
955 <0x0 0x2d 0x1>;
963 reg = <0x0 0x10510000 0x0 0x400>;
964 interrupts = <0x0 0x46 0x4>;
966 clocks = <&rtcclk 0>;
972 #size-cells = <0>;
973 reg = <0x0 0x17020000 0x0 0xd100>;
974 clocks = <&menetclk 0>;
980 reg = <0x0 0x17020000 0x0 0xd100>,
981 <0x0 0x17030000 0x0 0xc300>,
982 <0x0 0x10000000 0x0 0x200>;
984 interrupts = <0x0 0x3c 0x4>;
986 clocks = <&menetclk 0>;
994 #size-cells = <0>;
997 reg = <0x3>;
1006 reg = <0x0 0x1f210000 0x0 0xd100>,
1007 <0x0 0x1f200000 0x0 0xc300>,
1008 <0x0 0x1b000000 0x0 0x200>;
1010 interrupts = <0x0 0xa0 0x4>,
1011 <0x0 0xa1 0x4>;
1013 clocks = <&sge0clk 0>;
1022 reg = <0x0 0x1f210030 0x0 0xd100>,
1023 <0x0 0x1f200000 0x0 0xc300>,
1024 <0x0 0x1b000000 0x0 0x8000>;
1026 interrupts = <0x0 0xac 0x4>,
1027 <0x0 0xad 0x4>;
1038 reg = <0x0 0x1f610000 0x0 0xd100>,
1039 <0x0 0x1f600000 0x0 0xc300>,
1040 <0x0 0x18000000 0x0 0x200>;
1042 interrupts = <0x0 0x60 0x4>,
1043 <0x0 0x61 0x4>,
1044 <0x0 0x62 0x4>,
1045 <0x0 0x63 0x4>,
1046 <0x0 0x64 0x4>,
1047 <0x0 0x65 0x4>,
1048 <0x0 0x66 0x4>,
1049 <0x0 0x67 0x4>;
1050 channel = <0>;
1052 clocks = <&xge0clk 0>;
1061 reg = <0x0 0x1f620000 0x0 0xd100>,
1062 <0x0 0x1f600000 0x0 0xc300>,
1063 <0x0 0x18000000 0x0 0x8000>;
1065 interrupts = <0x0 0x6c 0x4>,
1066 <0x0 0x6d 0x4>;
1069 clocks = <&xge1clk 0>;
1077 reg = <0x0 0x10520000 0x0 0x100>;
1078 interrupts = <0x0 0x41 0x4>;
1079 clocks = <&rngpkaclk 0>;
1085 reg = <0x0 0x1f270000 0x0 0x10000>,
1086 <0x0 0x1f200000 0x0 0x10000>,
1087 <0x0 0x1b000000 0x0 0x400000>,
1088 <0x0 0x1054a000 0x0 0x100>;
1089 interrupts = <0x0 0x82 0x4>,
1090 <0x0 0xb8 0x4>,
1091 <0x0 0xb9 0x4>,
1092 <0x0 0xba 0x4>,
1093 <0x0 0xbb 0x4>;
1095 clocks = <&dmaclk 0>;