Lines Matching +full:0 +full:x1f200000
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
26 clocks = <&pmd0clk 0>;
31 reg = <0x0 0x001>;
33 cpu-release-addr = <0x1 0x0000fff8>;
36 clocks = <&pmd0clk 0>;
41 reg = <0x0 0x100>;
43 cpu-release-addr = <0x1 0x0000fff8>;
46 clocks = <&pmd1clk 0>;
51 reg = <0x0 0x101>;
53 cpu-release-addr = <0x1 0x0000fff8>;
56 clocks = <&pmd1clk 0>;
61 reg = <0x0 0x200>;
63 cpu-release-addr = <0x1 0x0000fff8>;
66 clocks = <&pmd2clk 0>;
71 reg = <0x0 0x201>;
73 cpu-release-addr = <0x1 0x0000fff8>;
76 clocks = <&pmd2clk 0>;
81 reg = <0x0 0x300>;
83 cpu-release-addr = <0x1 0x0000fff8>;
86 clocks = <&pmd3clk 0>;
91 reg = <0x0 0x301>;
93 cpu-release-addr = <0x1 0x0000fff8>;
96 clocks = <&pmd3clk 0>;
98 xgene_L2_0: l2-cache-0 {
118 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
119 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
120 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
121 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
122 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
123 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
124 v2m0: v2m@0 {
127 reg = <0x0 0x0 0x0 0x1000>;
132 reg = <0x0 0x10000 0x0 0x1000>;
137 reg = <0x0 0x20000 0x0 0x1000>;
142 reg = <0x0 0x30000 0x0 0x1000>;
147 reg = <0x0 0x40000 0x0 0x1000>;
152 reg = <0x0 0x50000 0x0 0x1000>;
157 reg = <0x0 0x60000 0x0 0x1000>;
162 reg = <0x0 0x70000 0x0 0x1000>;
167 reg = <0x0 0x80000 0x0 0x1000>;
172 reg = <0x0 0x90000 0x0 0x1000>;
177 reg = <0x0 0xa0000 0x0 0x1000>;
182 reg = <0x0 0xb0000 0x0 0x1000>;
187 reg = <0x0 0xc0000 0x0 0x1000>;
192 reg = <0x0 0xd0000 0x0 0x1000>;
197 reg = <0x0 0xe0000 0x0 0x1000>;
202 reg = <0x0 0xf0000 0x0 0x1000>;
208 interrupts = <1 12 0xff04>;
213 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
214 <1 13 0xff08>, /* Non-secure Phys IRQ */
215 <1 14 0xff08>, /* Virt IRQ */
216 <1 15 0xff08>; /* Hyp IRQ */
241 clocks = <&refclk 0>;
242 reg = <0x0 0x170000f0 0x0 0x10>;
249 clocks = <&pmdpll 0>;
250 reg = <0x0 0x7e200200 0x0 0x10>;
257 clocks = <&pmdpll 0>;
258 reg = <0x0 0x7e200210 0x0 0x10>;
265 clocks = <&pmdpll 0>;
266 reg = <0x0 0x7e200220 0x0 0x10>;
273 clocks = <&pmdpll 0>;
274 reg = <0x0 0x7e200230 0x0 0x10>;
281 clocks = <&refclk 0>;
282 reg = <0x0 0x17000120 0x0 0x1000>;
289 clocks = <&socpll 0>;
298 clocks = <&socplldiv2 0>;
299 reg = <0x0 0x17000000 0x0 0x2000>;
301 divider-offset = <0x164>;
302 divider-width = <0x5>;
303 divider-shift = <0x0>;
310 clocks = <&ahbclk 0>;
311 reg = <0x0 0x1704c000 0x0 0x2000>;
313 divider-offset = <0x10>;
314 divider-width = <0x2>;
315 divider-shift = <0x0>;
322 clocks = <&socplldiv2 0>;
323 reg = <0x0 0x1f2ac000 0x0 0x1000
324 0x0 0x17000000 0x0 0x2000>;
326 csr-offset = <0x0>;
327 csr-mask = <0x2>;
328 enable-offset = <0x8>;
329 enable-mask = <0x2>;
330 divider-offset = <0x178>;
331 divider-width = <0x8>;
332 divider-shift = <0x0>;
339 clocks = <&socplldiv2 0>;
340 reg = <0x0 0x1f2bc000 0x0 0x1000>;
348 clocks = <&socplldiv2 0>;
349 reg = <0x0 0x1f2cc000 0x0 0x1000>;
357 clocks = <&socplldiv2 0>;
358 reg = <0x0 0x1f61c000 0x0 0x1000>;
360 enable-mask = <0x3>;
361 csr-mask = <0x3>;
368 clocks = <&socplldiv2 0>;
369 reg = <0x0 0x1f62c000 0x0 0x1000>;
371 enable-mask = <0x3>;
372 csr-mask = <0x3>;
379 clocks = <&socplldiv2 0>;
380 reg = <0x0 0x17000000 0x0 0x2000>;
382 csr-offset = <0xc>;
383 csr-mask = <0x10>;
384 enable-offset = <0x10>;
385 enable-mask = <0x10>;
392 clocks = <&sbapbclk 0>;
393 reg = <0x0 0x1704c000 0x0 0x1000>;
395 csr-offset = <0x0>;
396 csr-mask = <0x40>;
397 enable-offset = <0x8>;
398 enable-mask = <0x40>;
405 reg = <0x0 0x17000000 0x0 0x400>;
411 offset = <0x14>;
412 mask = <0x1>;
417 reg = <0x0 0x7e200000 0x0 0x1000>;
422 reg = <0x0 0x7e700000 0x0 0x1000>;
427 reg = <0x0 0x7e720000 0x0 0x1000>;
432 reg = <0x0 0x1054a000 0x0 0x20>;
444 reg = <0x0 0x78800000 0x0 0x100>;
445 interrupts = <0x0 0x20 0x4>,
446 <0x0 0x21 0x4>,
447 <0x0 0x27 0x4>;
451 reg = <0x0 0x7e800000 0x0 0x1000>;
452 memory-controller = <0>;
457 reg = <0x0 0x7e840000 0x0 0x1000>;
463 reg = <0x0 0x7e880000 0x0 0x1000>;
469 reg = <0x0 0x7e8c0000 0x0 0x1000>;
475 reg = <0x0 0x7c000000 0x0 0x200000>;
476 pmd-controller = <0>;
481 reg = <0x0 0x7c200000 0x0 0x200000>;
487 reg = <0x0 0x7c400000 0x0 0x200000>;
493 reg = <0x0 0x7c600000 0x0 0x200000>;
499 reg = <0x0 0x7e600000 0x0 0x1000>;
504 reg = <0x0 0x7e930000 0x0 0x1000>;
516 reg = <0x0 0x78810000 0x0 0x1000>;
517 interrupts = <0x0 0x22 0x4>;
521 reg = <0x0 0x7e610000 0x0 0x1000>;
526 reg = <0x0 0x7e940000 0x0 0x1000>;
531 reg = <0x0 0x7e710000 0x0 0x1000>;
532 enable-bit-index = <0>;
537 reg = <0x0 0x7e730000 0x0 0x1000>;
543 reg = <0x0 0x7e810000 0x0 0x1000>;
544 enable-bit-index = <0>;
549 reg = <0x0 0x7e850000 0x0 0x1000>;
555 reg = <0x0 0x7e890000 0x0 0x1000>;
561 reg = <0x0 0x7e8d0000 0x0 0x1000>;
568 reg = <0x0 0x10540000 0x0 0x8000>;
570 interrupts = <0x0 0x0 0x4
571 0x0 0x1 0x4
572 0x0 0x2 0x4
573 0x0 0x3 0x4
574 0x0 0x4 0x4
575 0x0 0x5 0x4
576 0x0 0x6 0x4
577 0x0 0x7 0x4>;
582 mboxes = <&mailbox 0>;
593 reg = <0 0x10600000 0x0 0x1000>;
597 interrupts = <0x0 0x4c 0x4>;
604 reg = <0x0 0x19000000 0x0 0x100000>;
605 interrupts = <0x0 0x5d 0x4>;
617 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
618 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
620 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
621 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
622 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
624 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
625 bus-range = <0x00 0xff>;
626 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
628 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
629 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
630 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
632 clocks = <&pcie0clk 0>;
643 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
644 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
646 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
647 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
648 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
650 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
651 bus-range = <0x00 0xff>;
652 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
654 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
655 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
656 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
658 clocks = <&pcie1clk 0>;
664 reg = <0x0 0x1a000000 0x0 0x1000>,
665 <0x0 0x1f200000 0x0 0x1000>,
666 <0x0 0x1f20d000 0x0 0x1000>,
667 <0x0 0x1f20e000 0x0 0x1000>;
668 interrupts = <0x0 0x5a 0x4>;
674 reg = <0x0 0x1a200000 0x0 0x1000>,
675 <0x0 0x1f210000 0x0 0x1000>,
676 <0x0 0x1f21d000 0x0 0x1000>,
677 <0x0 0x1f21e000 0x0 0x1000>;
678 interrupts = <0x0 0x5b 0x4>;
684 reg = <0x0 0x1a400000 0x0 0x1000>,
685 <0x0 0x1f220000 0x0 0x1000>,
686 <0x0 0x1f22d000 0x0 0x1000>,
687 <0x0 0x1f22e000 0x0 0x1000>;
688 interrupts = <0x0 0x5c 0x4>;
694 reg = <0x0 0x1c000000 0x0 0x100>;
695 interrupts = <0x0 0x49 0x4>;
699 clocks = <&sdioclk 0>, <&ahbclk 0>;
704 reg = <0x0 0x1f63c000 0x0 0x40>;
711 reg = <0x0 0x1c024000 0x0 0x1000>;
713 #size-cells = <0>;
715 porta: gpio-controller@0 {
720 reg = <0>;
726 reg = <0x0 0x17001000 0x0 0x400>;
729 interrupts = <0x0 0x28 0x1>,
730 <0x0 0x29 0x1>,
731 <0x0 0x2a 0x1>,
732 <0x0 0x2b 0x1>,
733 <0x0 0x2c 0x1>,
734 <0x0 0x2d 0x1>,
735 <0x0 0x2e 0x1>,
736 <0x0 0x2f 0x1>;
748 #size-cells = <0>;
749 reg = <0x0 0x1f610000 0x0 0xd100>;
750 clocks = <&xge0clk 0>;
756 reg = <0x0 0x1f610000 0x0 0xd100>,
757 <0x0 0x1f600000 0x0 0xd100>,
758 <0x0 0x20000000 0x0 0x20000>;
759 interrupts = <0 96 4>,
760 <0 97 4>;
762 clocks = <&xge0clk 0>;
771 reg = <0x0 0x1f620000 0x0 0x10000>,
772 <0x0 0x1f600000 0x0 0xd100>,
773 <0x0 0x20000000 0x0 0x220000>;
774 interrupts = <0 108 4>,
775 <0 109 4>,
776 <0 110 4>,
777 <0 111 4>,
778 <0 112 4>,
779 <0 113 4>,
780 <0 114 4>,
781 <0 115 4>;
785 clocks = <&xge1clk 0>;
792 reg = <0x0 0x10520000 0x0 0x100>;
793 interrupts = <0x0 0x41 0x4>;
794 clocks = <&rngpkaclk 0>;
799 #size-cells = <0>;
801 reg = <0x0 0x10511000 0x0 0x1000>;
802 interrupts = <0 0x45 0x4>;
804 clocks = <&sbapbclk 0>;
810 #size-cells = <0>;
812 reg = <0x0 0x10640000 0x0 0x1000>;
813 interrupts = <0 0x3a 0x4>;
814 clocks = <&i2c4clk 0>;