Lines Matching +full:0 +full:x01c02000
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&ths 0>;
221 polling-delay-passive = <0>;
222 polling-delay = <0>;
228 polling-delay-passive = <0>;
229 polling-delay = <0>;
242 reg = <0x1000000 0x400000>;
246 ranges = <0 0x1000000 0x400000>;
248 display_clocks: clock@0 {
250 reg = <0x0 0x10000>;
263 reg = <0x20000 0x10000>;
273 compatible = "allwinner,sun50i-a64-de2-mixer-0";
274 reg = <0x100000 0x100000>;
283 #size-cells = <0>;
287 #size-cells = <0>;
290 mixer0_out_tcon0: endpoint@0 {
291 reg = <0>;
305 reg = <0x200000 0x100000>;
314 #size-cells = <0>;
318 #size-cells = <0>;
321 mixer1_out_tcon0: endpoint@0 {
322 reg = <0>;
337 reg = <0x01c00000 0x1000>;
344 reg = <0x00018000 0x28000>;
347 ranges = <0 0x00018000 0x28000>;
349 de2_sram: sram-section@0 {
351 reg = <0x0000 0x28000>;
357 reg = <0x01d00000 0x40000>;
360 ranges = <0 0x01d00000 0x40000>;
362 ve_sram: sram-section@0 {
365 reg = <0x000000 0x40000>;
372 reg = <0x01c02000 0x1000>;
384 reg = <0x01c0c000 0x1000>;
389 #clock-cells = <0>;
395 #size-cells = <0>;
397 tcon0_in: port@0 {
399 #size-cells = <0>;
400 reg = <0>;
402 tcon0_in_mixer0: endpoint@0 {
403 reg = <0>;
415 #size-cells = <0>;
430 reg = <0x01c0d000 0x1000>;
439 #size-cells = <0>;
441 tcon1_in: port@0 {
443 #size-cells = <0>;
444 reg = <0>;
446 tcon1_in_mixer0: endpoint@0 {
447 reg = <0>;
459 #size-cells = <0>;
472 reg = <0x01c0e000 0x1000>;
483 reg = <0x01c0f000 0x1000>;
492 #size-cells = <0>;
497 reg = <0x01c10000 0x1000>;
506 #size-cells = <0>;
511 reg = <0x01c11000 0x1000>;
520 #size-cells = <0>;
525 reg = <0x1c14000 0x400>;
530 reg = <0x34 0x8>;
536 reg = <0x01c15000 0x1000>;
546 reg = <0x01c17000 0x1000>;
555 reg = <0x01c19000 0x0400>;
560 phys = <&usbphy 0>;
562 extcon = <&usbphy 0>;
569 reg = <0x01c19400 0x14>,
570 <0x01c1a800 0x4>,
571 <0x01c1b800 0x4>;
589 reg = <0x01c1a000 0x100>;
601 reg = <0x01c1a400 0x100>;
611 reg = <0x01c1b000 0x100>;
625 reg = <0x01c1b400 0x100>;
637 reg = <0x01c20000 0x400>;
638 clocks = <&osc24M>, <&rtc 0>;
646 reg = <0x01c20800 0x400>;
650 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
798 #sound-dai-cells = <0>;
801 reg = <0x01c21000 0x400>;
809 pinctrl-0 = <&spdif_tx_pin>;
816 reg = <0x01c21800 0x400>;
822 #sound-dai-cells = <0>;
825 reg = <0x01c22000 0x400>;
836 #sound-dai-cells = <0>;
839 reg = <0x01c22400 0x400>;
850 #sound-dai-cells = <0>;
852 reg = <0x01c22c00 0x200>;
863 #sound-dai-cells = <0>;
866 reg = <0x01c22e00 0x600>;
875 reg = <0x01c25000 0x100>;
887 reg = <0x01c28000 0x400>;
888 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
898 reg = <0x01c28400 0x400>;
909 reg = <0x01c28800 0x400>;
920 reg = <0x01c28c00 0x400>;
931 reg = <0x01c29000 0x400>;
942 reg = <0x01c2ac00 0x400>;
947 pinctrl-0 = <&i2c0_pins>;
950 #size-cells = <0>;
955 reg = <0x01c2b000 0x400>;
960 pinctrl-0 = <&i2c1_pins>;
963 #size-cells = <0>;
968 reg = <0x01c2b400 0x400>;
973 pinctrl-0 = <&i2c2_pins>;
976 #size-cells = <0>;
981 reg = <0x01c68000 0x1000>;
988 pinctrl-0 = <&spi0_pins>;
993 #size-cells = <0>;
998 reg = <0x01c69000 0x1000>;
1005 pinctrl-0 = <&spi1_pins>;
1010 #size-cells = <0>;
1016 reg = <0x01c30000 0x10000>;
1028 #size-cells = <0>;
1034 reg = <0x01c40000 0x10000>;
1056 reg = <0x01c81000 0x1000>,
1057 <0x01c82000 0x2000>,
1058 <0x01c84000 0x2000>,
1059 <0x01c86000 0x2000>;
1068 reg = <0x01c21400 0x400>;
1071 pinctrl-0 = <&pwm_pin>;
1078 reg = <0x01c62000 0x1000>;
1082 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1088 reg = <0x01cb0000 0x1000>;
1096 pinctrl-0 = <&csi_pins>;
1102 reg = <0x01ca0000 0x1000>;
1110 #size-cells = <0>;
1122 reg = <0x01ca1000 0x1000>;
1128 #phy-cells = <0>;
1134 reg = <0x01e00000 0x20000>;
1148 reg = <0x01ee0000 0x10000>;
1162 #size-cells = <0>;
1164 hdmi_in: port@0 {
1165 reg = <0>;
1180 reg = <0x01ef0000 0x10000>;
1183 clock-names = "bus", "mod", "pll-0";
1186 #phy-cells = <0>;
1192 reg = <0x01f00000 0x400>;
1205 reg = <0x01f00c00 0x400>;
1211 reg = <0x01f01400 0x100>;
1212 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1221 reg = <0x01f015c0 0x4>;
1228 reg = <0x01f02400 0x400>;
1234 #size-cells = <0>;
1240 reg = <0x01f02000 0x400>;
1246 pinctrl-0 = <&r_ir_rx_pin>;
1253 reg = <0x01f03800 0x400>;
1256 pinctrl-0 = <&r_pwm_pin>;
1263 reg = <0x01f02c00 0x400>;
1295 reg = <0x01f03400 0x400>;
1301 pinctrl-0 = <&r_rsb_pins>;
1304 #size-cells = <0>;
1310 reg = <0x01c20ca0 0x20>;