Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ccu
1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a53";
25 enable-method = "psci";
29 compatible = "arm,cortex-a53";
32 enable-method = "psci";
36 compatible = "arm,cortex-a53";
39 enable-method = "psci";
43 compatible = "arm,cortex-a53";
46 enable-method = "psci";
51 compatible = "arm,psci-1.0";
55 dcxo24M: dcxo24M-clk {
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 clock-output-names = "dcxo24M";
59 #clock-cells = <0>;
62 iosc: internal-osc-clk {
63 compatible = "fixed-clock";
64 clock-frequency = <16000000>;
65 clock-accuracy = <300000000>;
66 clock-output-names = "iosc";
67 #clock-cells = <0>;
70 osc32k: osc32k-clk {
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
73 clock-output-names = "osc32k";
74 #clock-cells = <0>;
78 compatible = "arm,armv8-timer";
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
95 ccu: clock@3001000 { label
96 compatible = "allwinner,sun50i-a100-ccu";
99 clock-names = "hosc", "losc", "iosc";
100 #clock-cells = <1>;
101 #reset-cells = <1>;
104 gic: interrupt-controller@3021000 {
105 compatible = "arm,gic-400";
110 interrupt-controller;
111 #interrupt-cells = <3>;
115 compatible = "allwinner,sun50i-a100-sid",
116 "allwinner,sun50i-a64-sid";
118 #address-cells = <1>;
119 #size-cells = <1>;
127 compatible = "allwinner,sun50i-a100-pinctrl";
136 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
137 clock-names = "apb", "hosc", "losc";
138 gpio-controller;
139 #gpio-cells = <3>;
140 interrupt-controller;
141 #interrupt-cells = <3>;
143 uart0_pb_pins: uart0-pb-pins {
150 compatible = "snps,dw-apb-uart";
153 reg-shift = <2>;
154 reg-io-width = <4>;
155 clocks = <&ccu CLK_BUS_UART0>;
156 resets = <&ccu RST_BUS_UART0>;
161 compatible = "snps,dw-apb-uart";
164 reg-shift = <2>;
165 reg-io-width = <4>;
166 clocks = <&ccu CLK_BUS_UART1>;
167 resets = <&ccu RST_BUS_UART1>;
172 compatible = "snps,dw-apb-uart";
175 reg-shift = <2>;
176 reg-io-width = <4>;
177 clocks = <&ccu CLK_BUS_UART2>;
178 resets = <&ccu RST_BUS_UART2>;
183 compatible = "snps,dw-apb-uart";
186 reg-shift = <2>;
187 reg-io-width = <4>;
188 clocks = <&ccu CLK_BUS_UART3>;
189 resets = <&ccu RST_BUS_UART3>;
194 compatible = "snps,dw-apb-uart";
197 reg-shift = <2>;
198 reg-io-width = <4>;
199 clocks = <&ccu CLK_BUS_UART4>;
200 resets = <&ccu RST_BUS_UART4>;
205 compatible = "allwinner,sun50i-a100-i2c",
206 "allwinner,sun6i-a31-i2c";
209 clocks = <&ccu CLK_BUS_I2C0>;
210 resets = <&ccu RST_BUS_I2C0>;
212 #address-cells = <1>;
213 #size-cells = <0>;
217 compatible = "allwinner,sun50i-a100-i2c",
218 "allwinner,sun6i-a31-i2c";
221 clocks = <&ccu CLK_BUS_I2C1>;
222 resets = <&ccu RST_BUS_I2C1>;
224 #address-cells = <1>;
225 #size-cells = <0>;
229 compatible = "allwinner,sun50i-a100-i2c",
230 "allwinner,sun6i-a31-i2c";
233 clocks = <&ccu CLK_BUS_I2C2>;
234 resets = <&ccu RST_BUS_I2C2>;
236 #address-cells = <1>;
237 #size-cells = <0>;
241 compatible = "allwinner,sun50i-a100-i2c",
242 "allwinner,sun6i-a31-i2c";
245 clocks = <&ccu CLK_BUS_I2C3>;
246 resets = <&ccu RST_BUS_I2C3>;
248 #address-cells = <1>;
249 #size-cells = <0>;
252 ths: thermal-sensor@5070400 {
253 compatible = "allwinner,sun50i-a100-ths";
256 clocks = <&ccu CLK_BUS_THS>;
257 clock-names = "bus";
258 resets = <&ccu RST_BUS_THS>;
259 nvmem-cells = <&ths_calibration>;
260 nvmem-cell-names = "calibration";
261 #thermal-sensor-cells = <1>;
265 compatible = "allwinner,sun50i-a100-r-ccu";
268 <&ccu CLK_PLL_PERIPH0>;
269 clock-names = "hosc", "losc", "iosc", "pll-periph";
270 #clock-cells = <1>;
271 #reset-cells = <1>;
274 r_intc: interrupt-controller@7010320 {
275 compatible = "allwinner,sun50i-a100-nmi",
276 "allwinner,sun9i-a80-nmi";
277 interrupt-controller;
278 #interrupt-cells = <2>;
284 compatible = "allwinner,sun50i-a100-r-pinctrl";
288 clock-names = "apb", "hosc", "losc";
289 gpio-controller;
290 #gpio-cells = <3>;
291 interrupt-controller;
292 #interrupt-cells = <3>;
294 r_i2c0_pins: r-i2c0-pins {
299 r_i2c1_pins: r-i2c1-pins {
306 compatible = "snps,dw-apb-uart";
309 reg-shift = <2>;
310 reg-io-width = <4>;
317 compatible = "allwinner,sun50i-a100-i2c",
318 "allwinner,sun6i-a31-i2c";
323 pinctrl-names = "default";
324 pinctrl-0 = <&r_i2c0_pins>;
326 #address-cells = <1>;
327 #size-cells = <0>;
331 compatible = "allwinner,sun50i-a100-i2c",
332 "allwinner,sun6i-a31-i2c";
337 pinctrl-names = "default";
338 pinctrl-0 = <&r_i2c1_pins>;
340 #address-cells = <1>;
341 #size-cells = <0>;
345 thermal-zones {
346 cpu-thermal-zone {
347 polling-delay-passive = <0>;
348 polling-delay = <0>;
349 thermal-sensors = <&ths 0>;
352 ddr-thermal-zone {
353 polling-delay-passive = <0>;
354 polling-delay = <0>;
355 thermal-sensors = <&ths 2>;
358 gpu-thermal-zone {
359 polling-delay-passive = <0>;
360 polling-delay = <0>;
361 thermal-sensors = <&ths 1>;