Lines Matching +full:default +full:- +full:on
1 # SPDX-License-Identifier: GPL-2.0-only
161 if $(cc-option,-fpatchable-function-entry=2)
205 ARM 64-bit (AArch64) Linux support.
215 default 16 if ARM64_64K_PAGES
216 default 14 if ARM64_16K_PAGES
217 default 12
221 default 5 if ARM64_64K_PAGES
222 default 7 if ARM64_16K_PAGES
223 default 4
227 default 5 if ARM64_64K_PAGES
228 default 5 if ARM64_16K_PAGES
229 default 4
232 default 14 if ARM64_64K_PAGES
233 default 16 if ARM64_16K_PAGES
234 default 18
237 # VA_BITS - PAGE_SHIFT - 3
239 default 19 if ARM64_VA_BITS=36
240 default 24 if ARM64_VA_BITS=39
241 default 27 if ARM64_VA_BITS=42
242 default 30 if ARM64_VA_BITS=47
243 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
244 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
245 default 33 if ARM64_VA_BITS=48
246 default 14 if ARM64_64K_PAGES
247 default 16 if ARM64_16K_PAGES
248 default 18
251 default 7 if ARM64_64K_PAGES
252 default 9 if ARM64_16K_PAGES
253 default 11
256 default 16
266 default 0xdead000000000000
276 depends on BUG
280 depends on GENERIC_BUG
293 default y
297 default y
316 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
317 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
318 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
319 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
320 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
321 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
330 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
334 depends on KASAN
335 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
336 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
337 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
338 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
339 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
340 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
341 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
342 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
343 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
344 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
345 default 0xffffffffffffffff
357 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
358 default y
362 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
365 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
367 not progress on read data presented on the read data channel and the
371 data cache clean-and-invalidate.
373 as it depends on the alternative framework, which will only patch
379 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
380 default y
384 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
389 on the AMBA 5 CHI interface, which can cause data corruption if the
393 data cache clean-and-invalidate.
395 as it depends on the alternative framework, which will only patch
401 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
402 default y
406 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
409 If a Cortex-A53 processor is executing a store or prefetch for
416 data cache clean-and-invalidate.
418 workaround, as it depends on the alternative framework, which will
424 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
425 default y
429 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
438 data cache clean-and-invalidate.
440 as it depends on the alternative framework, which will only patch
446 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
447 default y
450 erratum 832075 on Cortex-A57 parts up to r1p2.
452 Affected Cortex-A57 parts might deadlock when exclusive load/store
453 instructions to Write-Back memory are mixed with Device loads.
455 The workaround is to promote device loads to use Load-Acquire
458 as it depends on the alternative framework, which will only patch
464 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
465 depends on KVM
466 default y
469 erratum 834220 on Cortex-A57 parts up to r1p2.
471 Affected Cortex-A57 parts might report a Stage 2 translation
479 as it depends on the alternative framework, which will only patch
485 bool "Cortex-A53: 845719: a load might read incorrect data"
486 depends on COMPAT
487 default y
490 erratum 845719 on Cortex-A53 parts up to r0p4.
492 When running a compat (AArch32) userspace on an affected Cortex-A53
497 The workaround is to write the contextidr_el1 register on exception
498 return to a 32-bit task.
500 as it depends on the alternative framework, which will only patch
506 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
507 default y
510 This option links the kernel with '--fix-cortex-a53-843419' and
512 cause subsequent memory accesses to use an incorrect address on
513 Cortex-A53 parts up to r0p4.
518 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
519 default y
521 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
523 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
525 without a break-before-make. The workaround is to disable the usage
526 of hardware DBM locally on the affected cores. CPUs not affected by
532 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
533 default y
534 depends on COMPAT
536 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
539 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
549 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
550 default y
553 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
555 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
562 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
563 default y
566 This option adds work arounds for ARM Cortex-A57 erratum 1319537
569 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
575 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
576 default y
579 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
581 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
591 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
592 default y
595 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
597 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
601 break-before-make sequence, then under very rare circumstances
607 bool "Cortex-A76: Software Step might prevent interrupt recognition"
608 default y
610 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
612 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
625 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
626 default y
628 This option adds a workaround for ARM Neoverse-N1 erratum
631 Affected Neoverse-N1 cores could execute a stale instruction when
632 modified by another CPU. The workaround depends on a firmware
636 forces user-space to perform cache maintenance.
641 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
642 default y
644 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
646 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
647 of a store-exclusive or read of PAR_EL1 and a load with device or
648 non-cacheable memory attributes. The workaround depends on a firmware
662 default y
666 This implements two gicv3-its errata workarounds for ThunderX. Both
678 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
679 depends on NUMA
680 default y
688 default y
698 default y
700 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
702 contains data for a non-current ASID. The fix is to
709 default y
711 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
713 interrupts in host. Trapping both GICv3 group-0 and group-1
720 default y
722 On Cavium ThunderX2, a load, store or prefetch instruction between a
736 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
737 default y
739 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
740 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
744 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
745 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
746 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
747 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
750 The workaround only affects the Fujitsu-A64FX.
756 default y
766 default y
768 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
777 default y
780 On Falkor v1, the CPU may prematurely complete a DSB following a
788 default y
790 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
798 default y
807 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
808 default y
811 MSI doorbell writes with non-zero values for the device ID.
820 default ARM64_4K_PAGES
839 This feature enables 64KB pages support (4KB by default)
841 look-up. AArch32 emulation requires applications compiled
848 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
849 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
850 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
857 bool "36-bit" if EXPERT
858 depends on ARM64_16K_PAGES
861 bool "39-bit"
862 depends on ARM64_4K_PAGES
865 bool "42-bit"
866 depends on ARM64_64K_PAGES
869 bool "47-bit"
870 depends on ARM64_16K_PAGES
873 bool "48-bit"
876 bool "52-bit"
877 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
879 Enable 52-bit virtual addressing for userspace when explicitly
880 requested via a hint to mmap(). The kernel will also use 52-bit
882 this feature is available, otherwise it reverts to 48-bit).
884 NOTE: Enabling 52-bit virtual addressing in conjunction with
887 impact on its susceptibility to brute-force attacks.
889 If unsure, select 48-bit virtual addressing instead.
894 bool "Force 52-bit virtual addresses for userspace"
895 depends on ARM64_VA_BITS_52 && EXPERT
897 For systems with 52-bit userspace VAs enabled, the kernel will attempt
898 to maintain compatibility with older software by providing 48-bit VAs
901 This configuration option disables the 48-bit compatibility logic, and
902 forces all userspace addresses to be 52-bit on HW that supports it. One
908 default 36 if ARM64_VA_BITS_36
909 default 39 if ARM64_VA_BITS_39
910 default 42 if ARM64_VA_BITS_42
911 default 47 if ARM64_VA_BITS_47
912 default 48 if ARM64_VA_BITS_48
913 default 52 if ARM64_VA_BITS_52
917 default ARM64_PA_BITS_48
923 bool "48-bit"
926 bool "52-bit (ARMv8.2)"
927 depends on ARM64_64K_PAGES
928 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
930 Enable support for a 52-bit physical address space, introduced as
931 part of the ARMv8.2-LPA extension.
933 With this enabled, the kernel will also continue to work on CPUs that
934 do not support ARMv8.2-LPA, but with some added memory overhead (and
941 default 48 if ARM64_PA_BITS_48
942 default 52 if ARM64_PA_BITS_52
946 default CPU_LITTLE_ENDIAN
953 bool "Build big-endian kernel"
955 Say Y if you plan on running a kernel with a big-endian userspace.
958 bool "Build little-endian kernel"
960 Say Y if you plan on running a kernel with a little-endian userspace.
966 bool "Multi-core scheduler support"
968 Multi-core scheduler support improves the CPU scheduler's decision
969 making when dealing with multi-core CPU chips at a cost of slightly
980 int "Maximum number of CPUs (2-4096)"
982 default "256"
985 bool "Support for hot-pluggable CPUs"
988 Say Y here to experiment with turning CPUs off and on. CPUs
997 Enable NUMA (Non-Uniform Memory Access) support.
999 The kernel will try to allocate memory used by a CPU on the
1006 default "4"
1007 depends on NEED_MULTIPLE_NODES
1009 Specify the maximum number of NUMA Nodes available on the target
1014 depends on NUMA
1018 depends on NUMA
1022 depends on NUMA
1050 depends on ARM_PMU
1065 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1086 depends on PM_SLEEP_SMP
1106 depends on KEXEC_FILE
1118 default y
1119 depends on KEXEC_SIG
1120 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1125 depends on KEXEC_SIG
1126 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1133 loaded in the main kernel with kexec-tools into a specially
1137 For more details see Documentation/admin-guide/kdump/kdump.rst
1141 depends on XEN
1144 bool "Xen guest support on ARM64"
1145 depends on ARM64 && OF
1149 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1153 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1154 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1155 default "11"
1169 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1171 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1172 4M allocations matching the default size used by generic code.
1176 default y
1178 Speculation attacks against some high-performance processors can
1181 when running in userspace, mapping it back in on exception entry
1188 default y
1190 Apply read-only attributes of VM areas to the linear alias of
1191 the backing pages as well. This prevents code or read-only data
1194 be turned off at runtime by passing rodata=[off|on] (and turned on
1204 user-space memory directly by pointing TTBR0_EL1 to a reserved
1210 default y
1215 Documentation/arm64/tagged-address-abi.rst.
1218 bool "Kernel support for 32-bit EL0"
1219 depends on ARM64_4K_PAGES || EXPERT
1225 This option enables support for a 32-bit EL0 running under a 64-bit
1226 kernel at EL1. AArch32-specific components such as system calls,
1234 If you want to execute 32-bit userspace applications, say Y.
1239 bool "Enable kuser helpers page for 32-bit applications"
1240 default y
1242 Warning: disabling this option may break 32-bit user programs.
1247 the system. This permits binaries to be run on ARMv4 through
1256 If all of the binaries and libraries which run on your platform
1260 relying on those helpers is run, it will not function correctly.
1266 bool "Enable vDSO for 32-bit applications"
1267 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1269 default y
1271 Place in the process address space of 32-bit applications an
1275 You must have a 32-bit build of glibc 2.22 or later for programs
1279 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1280 depends on COMPAT_VDSO
1281 default y
1283 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1284 otherwise with '-marm'.
1288 depends on SYSCTL
1307 sysctl which is disabled by default.
1316 on an external transaction monitoring block called a global
1326 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1327 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1342 The SETEND instruction alters the data-endianness of the
1349 Note: All the cpus on the system must have mixed endian support at EL0
1350 for this feature to be enabled. If a new CPU - which doesn't support mixed
1351 endian - is hotplugged in after this feature has been enabled, there could
1363 default y
1367 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1370 Similarly, writes to read-only pages with the DBM bit set will
1371 clear the read-only bit (AP[2]) instead of raising a
1375 to work on pre-ARMv8.1 hardware and the performance impact is
1380 default y
1383 prevents the kernel or hypervisor from accessing user-space (EL0)
1394 default ARM64_USE_LSE_ATOMICS
1395 depends on $(as-instr,.arch_extension lse)
1399 depends on JUMP_LABEL
1400 default y
1406 Say Y here to make use of these instructions for the in-kernel
1407 atomic routines. This incurs a small overhead on CPUs that do
1414 default y
1417 directly at EL2 (instead of EL1) on processors that support
1431 default y
1438 variant of the load/store instructions. This ensures that user-space
1443 Choosing this option will cause copy_to_user() et al to use user-space
1455 Say Y to enable support for the persistent memory API based on the
1464 default y
1470 On CPUs with these extensions system software can use additional
1476 Platform RAS features may additionally depend on firmware support.
1480 default y
1481 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1498 default y
1499 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1502 depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1503 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1504 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1514 context-switched along with the process.
1516 If the compiler supports the -mbranch-protection or
1517 -msign-return-address flag (e.g. GCC 7 or later), then this option
1527 If the feature is present on the boot CPU but not on a late CPU, then
1530 but with the feature disabled. On such a system, this option should
1538 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1542 def_bool $(cc-option,-msign-return-address=all)
1545 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1548 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1556 default y
1562 To enable the use of this extension on CPUs that implement it, say Y.
1565 support when running on CPUs that present the activity monitors
1578 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1582 default y
1583 depends on AS_HAS_ARMV8_4
1585 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1597 default y
1603 To make use of BTI on CPUs that support it, say Y.
1619 default y
1620 depends on ARM64_BTI
1621 depends on ARM64_PTR_AUTH
1622 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1624 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1625 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1626 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1635 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1639 default y
1651 default y
1659 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1663 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1667 default y
1668 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1672 architectural support for run-time, always-on detection of
1674 to eliminate vulnerabilities arising from memory-unsafe
1682 not be allowed a late bring-up.
1688 Documentation/arm64/memory-tagging-extension.rst.
1694 default y
1695 depends on !KVM || ARM64_VHE
1702 To enable use of this extension on CPUs that implement it, say Y.
1704 On CPUs that support the SVE2 extensions, this option will enable
1708 support when running on SVE capable hardware. The required support
1718 If you need the kernel to boot on SVE-capable hardware with broken
1732 depends on MODULES
1751 bool "Support for NMI-like interrupts"
1754 Adds support for mimicking Non-Maskable Interrupts through the use of
1778 default y
1795 relying on knowledge of the location of kernel internals.
1798 random u64 value in /chosen/kaslr-seed at kernel entry.
1809 depends on RANDOMIZE_BASE
1810 default y
1823 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
1827 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1835 depends on ACPI
1843 string "Default kernel command string"
1844 default ""
1846 Provide a set of default command-line options at build time by
1851 bool "Always use the default kernel command string"
1852 depends on CMDLINE != ""
1854 Always use the default kernel command string, even if the boot
1857 command-line options your boot loader passes to the kernel.
1864 depends on OF && !CPU_BIG_ENDIAN
1865 depends on KERNEL_MODE_NEON
1873 default y
1876 by UEFI firmware (such as non-volatile variables, realtime
1879 is only useful on systems that have UEFI firmware.
1883 depends on EFI
1884 default y
1888 This option is only useful on systems that have UEFI firmware.
1890 continue to boot on existing non-UEFI platforms.
1896 depends on COMPAT && SYSVIPC
1900 depends on HUGETLB_PAGE && MIGRATION
1904 depends on TRANSPARENT_HUGEPAGE
1912 depends on CPU_PM
1916 depends on HIBERNATION