56 #define RD_BITS(i)	((i >> 12) & 15)	/* Rd			*/
72 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
182 #define TYPE_DONE	3
204 	"3:	mov	%0, #1\n"			\
208 	"	.align	3\n"				\
209 	"	.long	1b, 3b\n"			\
261 		"3:\n"						\
265 		"	b	3b\n"				\
268 		"	.align	3\n"				\
296 	 ARM(	"3:	"ins"	%1, [%2], #1\n"	)		\
297 	 THUMB(	"3:	"ins"	%1, [%2]\n"	)		\
308 		"	.align	3\n"				\
311 		"	.long	3b, 6b\n"			\
342 	unsigned int rd = RD_BITS(instr);  in do_alignment_ldrhstrh()  local
357 		regs->uregs[rd] = val;  in do_alignment_ldrhstrh()
359 		put16_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrhstrh()
375 		regs->uregs[rd] = val;  in do_alignment_ldrhstrh()
378 		put16t_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrhstrh()
391 	unsigned int rd = RD_BITS(instr);  in do_alignment_ldrdstrd()  local
399 	} else if (((rd & 1) == 1) || (rd == 14))  in do_alignment_ldrdstrd()
403 		rd2 = rd + 1;  in do_alignment_ldrdstrd()
414 		regs->uregs[rd] = val;  in do_alignment_ldrdstrd()
418 		put32_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrdstrd()
434 		regs->uregs[rd] = val;  in do_alignment_ldrdstrd()
438 		put32t_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrdstrd()
453 	unsigned int rd = RD_BITS(instr);  in do_alignment_ldrstr()  local
463 		regs->uregs[rd] = val;  in do_alignment_ldrstr()
465 		put32_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrstr()
474 		regs->uregs[rd] = val;  in do_alignment_ldrstr()
477 		put32t_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrstr()
502 	unsigned int rd, rn, correction, nr_regs, regbits;  in do_alignment_ldmstm()  local
550 		for (regbits = REGMASK_BITS(instr), rd = 0; regbits;  in do_alignment_ldmstm()
551 		     regbits >>= 1, rd += 1)  in do_alignment_ldmstm()
556 					regs->uregs[rd] = val;  in do_alignment_ldmstm()
558 					put32t_unaligned_check(regs->uregs[rd], eaddr);  in do_alignment_ldmstm()
563 		for (regbits = REGMASK_BITS(instr), rd = 0; regbits;  in do_alignment_ldmstm()
564 		     regbits >>= 1, rd += 1)  in do_alignment_ldmstm()
569 					regs->uregs[rd] = val;  in do_alignment_ldmstm()
571 					put32_unaligned_check(regs->uregs[rd], eaddr);  in do_alignment_ldmstm()
621 			((tinstr & (7<<0)) << (12-0)) |		/* Rd */  in thumb2arm()
622 			((tinstr & (7<<3)) << (16-3)) |		/* Rn */  in thumb2arm()
629 			((tinstr & (7<<0)) << (12-0)) |		/* Rd */  in thumb2arm()
630 			((tinstr & (7<<3)) << (16-3)) |		/* Rn */  in thumb2arm()
632 			((tinstr & (3<<9)) >> (9-8));	 /* immed_5[4:3] */  in thumb2arm()
649 			    ((tinstr & (7<<0)) << (12-0)) |	/* Rd */  in thumb2arm()
650 			    ((tinstr & (7<<3)) << (16-3)) |	/* Rn */  in thumb2arm()
654 	/* 6.5.1 Format 3: */  in thumb2arm()
655 	case 0x4800 >> 11:				/* 7.1.28 LDR(3) */  in thumb2arm()
662 		    ((tinstr & (7<<8)) << (12-8)) |		/* Rd */  in thumb2arm()
666 	case 0x9000 >> 11:				/* 7.1.54 STR(3) */  in thumb2arm()
670 			((tinstr & (7<<8)) << (12-8)) |		/* Rd */  in thumb2arm()
687 		if ((tinstr & (3 << 9)) == 0x0400) {  in thumb2arm()
715  * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
1035 	 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section  in alignment_init()
1042 		hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,  in alignment_init()