Lines Matching full:r1
160 cpu_to_csr_reg r1, r3
161 add r1, r1, r12 @ virtual CSR address for this CPU
178 str r12, [r1]
186 ldr r3, [r1] @ read CSR
187 str r3, [r1] @ clear CSR
259 mov32 r1, tegra30_iram_start
260 sub r0, r0, r1
261 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
262 add r0, r0, r1
323 mov r1, #(1 << 28)
324 str r1, [r0, #CLK_RESET_SCLK_BURST]
325 str r1, [r0, #CLK_RESET_CCLK_BURST]
326 mov r1, #0
327 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
328 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
334 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
335 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
336 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
339 ldr r1, [r7]
340 add r1, r1, #2
341 wait_until r1, r7, r3
345 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
346 orr r1, r1, #(1 << 12)
347 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
349 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
350 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
351 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
358 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
359 orr r1, r1, #(1 << 12)
360 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
362 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
363 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
366 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
367 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
369 pll_locked r1, r0, CLK_RESET_PLLM_BASE
370 pll_locked r1, r0, CLK_RESET_PLLP_BASE
371 pll_locked r1, r0, CLK_RESET_PLLA_BASE
372 pll_locked r1, r0, CLK_RESET_PLLC_BASE
379 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
380 cmp r1, #TEGRA30
383 pll_locked r1, r0, CLK_RESET_PLLX_BASE
385 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
386 bic r1, r1, #(1<<31) @ disable PllP bypass
387 str r1, [r0, #CLK_RESET_PLLP_BASE]
389 mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
390 str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
394 ldr r1, [r7]
395 add r1, r1, #LOCK_DELAY
396 wait_until r1, r7, r3
411 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
412 mvn r1, r1
413 bic r1, r1, #(1 << 31)
414 orr r1, r1, #(1 << 30)
415 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
428 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
429 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
430 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
431 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
432 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
433 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
436 ldr r1, [r0, #EMC_CFG_DIG_DLL]
437 orr r1, r1, #(1 << 30) @ set DLL_RESET
438 str r1, [r0, #EMC_CFG_DIG_DLL]
440 emc_timing_update r1, r0
443 movweq r1, #:lower16:TEGRA_EMC1_BASE
444 movteq r1, #:upper16:TEGRA_EMC1_BASE
445 cmpeq r0, r1
447 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
448 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
449 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
450 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
453 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
454 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
457 ldr r1, [r0, #EMC_CFG]
458 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
459 str r1, [r0, #EMC_CFG]
461 mov r1, #0
462 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
463 mov r1, #1
465 streq r1, [r0, #EMC_NOP]
466 streq r1, [r0, #EMC_NOP]
468 emc_device_mask r1, r0
472 ands r2, r2, r1
475 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
491 tst r1, #2
510 tst r1, #2
521 mov r1, #0 @ unstall all transactions
522 str r1, [r0, #EMC_REQ_CTRL]
523 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
524 str r1, [r0, #EMC_ZCAL_INTERVAL]
525 ldr r1, [r5, #0x0] @ restore EMC_CFG
526 str r1, [r0, #EMC_CFG]
528 emc_timing_update r1, r0
533 mov32 r1, TEGRA_EMC1_BASE
534 cmp r0, r1
535 movne r0, r1
626 ldr r1, [r7]
627 add r1, r1, #2
628 wait_until r1, r7, r9
640 ldr r1, [r7]
641 add r1, r1, #2
642 wait_until r1, r7, r9
650 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
651 cmp r1, #TEGRA30
672 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
694 cpu_id r1
696 cpu_to_csr_reg r2, r1
708 cpu_to_halt_reg r2, r1
753 ldr r1, [r0]
754 str r1, [r8, r9] @ save the content of the addr
772 mov r1, #0
773 str r1, [r0, #EMC_ZCAL_INTERVAL]
774 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
775 ldr r1, [r0, #EMC_CFG]
776 bic r1, r1, #(1 << 28)
777 bicne r1, r1, #(1 << 29)
778 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
780 emc_timing_update r1, r0
782 ldr r1, [r7]
783 add r1, r1, #5
784 wait_until r1, r7, r2
787 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
788 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
791 mov r1, #3
792 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
795 ldr r1, [r0, #EMC_EMC_STATUS]
796 tst r1, #4
799 mov r1, #1
800 str r1, [r0, #EMC_SELF_REF]
802 emc_device_mask r1, r0
806 and r2, r2, r1
807 cmp r2, r1
811 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
813 and r1, r1, r2
814 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
815 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
817 orreq r1, r1, #7 @ set E_NO_VTTGEN
818 orrne r1, r1, #0x3f
819 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
821 emc_timing_update r1, r0
826 mov32 r1, TEGRA_EMC1_BASE
827 cmp r0, r1
828 movne r0, r1
832 ldr r1, [r4, #PMC_CTRL]
833 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
839 mov32 r1, 0x8EC00000
840 str r1, [r4, #PMC_IO_DPD_REQ]