Lines Matching full:r0
69 cpu_id r0
77 * r0 is cpu to reset
85 * corrupts r0-r3, r12
88 cmp r0, #0
91 cpu_to_halt_reg r1, r0
99 mov r1, r1, lsl r0
105 cmp r3, r0
119 mov r4, r0
121 mov r0, #TEGRA_FLUSH_CACHE_ALL
123 mov r0, r4
126 add r3, r3, r0
128 mov32 r0, tegra20_tear_down_core
130 sub r0, r0, r1
132 add r0, r0, r1
171 mov32 r0, TEGRA_CLK_RESET_BASE
174 str r1, [r0, #CLK_RESET_SCLK_BURST]
175 str r1, [r0, #CLK_RESET_CCLK_BURST]
177 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
178 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
180 pll_enable r1, r0, CLK_RESET_PLLM_BASE
181 pll_enable r1, r0, CLK_RESET_PLLP_BASE
182 pll_enable r1, r0, CLK_RESET_PLLC_BASE
208 str r4, [r0, #CLK_RESET_SCLK_BURST]
210 str r4, [r0, #CLK_RESET_CCLK_BURST]
212 mov32 r0, TEGRA_EMC_BASE
213 ldr r1, [r0, #EMC_CFG]
215 str r1, [r0, #EMC_CFG]
218 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
220 str r1, [r0, #EMC_NOP]
221 str r1, [r0, #EMC_NOP]
223 emc_device_mask r1, r0
226 ldr r2, [r0, #EMC_EMC_STATUS]
231 str r1, [r0, #EMC_REQ_CTRL]
233 mov32 r0, TEGRA_PMC_BASE
234 ldr r0, [r0, #PMC_SCRATCH41]
235 ret r0 @ jump to tegra_resume
260 mov r0, #(1 << 28)
261 str r0, [r5, #CLK_RESET_SCLK_BURST]
262 str r0, [r5, #CLK_RESET_CCLK_BURST]
263 mov r0, #0
264 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
265 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
274 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
275 bic r0, r0, #(1 << 30)
276 str r0, [r5, #CLK_RESET_PLLM_BASE]
277 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
278 bic r0, r0, #(1 << 30)
279 str r0, [r5, #CLK_RESET_PLLP_BASE]
280 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
281 bic r0, r0, #(1 << 30)
282 str r0, [r5, #CLK_RESET_PLLC_BASE]
285 mov r0, #0 /* brust policy = 32KHz */
286 str r0, [r5, #CLK_RESET_SCLK_BURST]
300 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
301 orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
304 str r0, [r6, r1]
306 ldr r0, [r6, r1] /* memory barrier */
350 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
352 ldr r1, [r0]
356 str r1, [r0] @ set the save val to the addr
364 ldr r0, [r5, #CLK_RESET_SCLK_BURST]
366 str r0, [r2]