Lines Matching full:r1
91 cpu_to_halt_reg r1, r0
94 str r2, [r3, r1] @ put flow controller in wait event mode
95 ldr r2, [r3, r1]
98 movw r1, 0x1011
99 mov r1, r1, lsl r0
101 str r1, [r3, #0x340] @ put slave CPU in reset
129 mov32 r1, tegra20_iram_start
130 sub r0, r0, r1
131 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
132 add r0, r0, r1
173 mov r1, #(1 << 28)
174 str r1, [r0, #CLK_RESET_SCLK_BURST]
175 str r1, [r0, #CLK_RESET_CCLK_BURST]
176 mov r1, #0
177 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
178 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
180 pll_enable r1, r0, CLK_RESET_PLLM_BASE
181 pll_enable r1, r0, CLK_RESET_PLLP_BASE
182 pll_enable r1, r0, CLK_RESET_PLLC_BASE
192 ldr r1, [r4, r5]
193 str r1, [r7] @ restore the value in pad_save
202 ldr r1, [r7]
203 add r1, r1, #0xff
204 wait_until r1, r7, r9
213 ldr r1, [r0, #EMC_CFG]
214 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP
215 str r1, [r0, #EMC_CFG]
217 mov r1, #0
218 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
219 mov r1, #1
220 str r1, [r0, #EMC_NOP]
221 str r1, [r0, #EMC_NOP]
223 emc_device_mask r1, r0
227 ands r2, r2, r1
230 mov r1, #0 @ unstall all transactions
231 str r1, [r0, #EMC_REQ_CTRL]
269 ldr r1, [r7]
270 add r1, r1, #2
271 wait_until r1, r7, r9
302 cpu_id r1
303 cpu_to_halt_reg r1, r1
304 str r0, [r6, r1]
306 ldr r0, [r6, r1] /* memory barrier */
322 mov32 r1, TEGRA_EMC_BASE @ r1 reserved for emc base addr
325 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
328 ldr r2, [r1, #EMC_EMC_STATUS]
333 str r2, [r1, #EMC_SELF_REF]
335 emc_device_mask r2, r1
338 ldr r3, [r1, #EMC_EMC_STATUS]
352 ldr r1, [r0]
353 str r1, [r4, r5] @ save the content of the addr
355 ldr r1, [r3, r5]
356 str r1, [r0] @ set the save val to the addr