Lines Matching +full:s3c6400 +full:- +full:pwm
1 // SPDX-License-Identifier: GPL-2.0
28 #include <linux/dma-mapping.h>
31 #include <linux/irqchip/arm-vic.h>
40 #include "regs-gpio.h"
41 #include "gpio-samsung.h"
46 #include "gpio-cfg.h"
47 #include "pwm-core.h"
48 #include "regs-irqtype.h"
50 #include "irq-uart-s3c64xx.h"
70 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); in s3c64xx_init_uarts()
75 static const char name_s3c6400[] = "S3C6400";
161 .name = "s3c64xx-core",
162 .dev_name = "s3c64xx-core",
178 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; in s3c64xx_set_timer_source()
225 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
226 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
227 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
228 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
229 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
230 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
243 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
251 mask |= (u32)data->chip_data; in s3c_irq_eint_mask()
260 mask &= ~((u32)data->chip_data); in s3c_irq_eint_unmask()
266 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND); in s3c_irq_eint_ack()
271 /* compiler should in-line these */ in s3c_irq_eint_maskack()
278 int offs = eint_offset(data->irq); in s3c_irq_eint_set_type()
286 return -EINVAL; in s3c_irq_eint_set_type()
320 return -1; in s3c_irq_eint_set_type()
326 shift = ((offs - 16) / 2) * 4; in s3c_irq_eint_set_type()
340 pin = S3C64XX_GPL(offs + 8 - 16); in s3c_irq_eint_set_type()
343 pin = S3C64XX_GPM(offs - 23); in s3c_irq_eint_set_type()
353 .name = "s3c-eint",
376 status &= (1 << (end - start + 1)) - 1; in s3c_irq_demux_eint()
410 /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */ in s3c64xx_init_irq_eint()
412 return -ENODEV; in s3c64xx_init_irq_eint()