Lines Matching +full:irqs +full:- +full:reserved
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2003-2004 Simtec Electronics
28 #include <mach/irqs.h>
29 #include "regs-irq.h"
30 #include "regs-gpio.h"
33 #include "regs-irqtype.h"
54 * @reg_pending register holding pending irqs
58 * @parent parent controller for ext and sub irqs
59 * @irqs irq-data, always s3c_irq_data[32]
67 struct s3c_irq_data *irqs; member
81 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_mask()
82 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_mask()
87 mask = readl_relaxed(intc->reg_mask); in s3c_irq_mask()
88 mask |= (1UL << irq_data->offset); in s3c_irq_mask()
89 writel_relaxed(mask, intc->reg_mask); in s3c_irq_mask()
92 parent_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c_irq_mask()
98 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { in s3c_irq_mask()
99 irqno = irq_find_mapping(parent_intc->domain, in s3c_irq_mask()
100 irq_data->parent_irq); in s3c_irq_mask()
109 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_unmask()
110 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_unmask()
114 mask = readl_relaxed(intc->reg_mask); in s3c_irq_unmask()
115 mask &= ~(1UL << irq_data->offset); in s3c_irq_unmask()
116 writel_relaxed(mask, intc->reg_mask); in s3c_irq_unmask()
119 irqno = irq_find_mapping(parent_intc->domain, in s3c_irq_unmask()
120 irq_data->parent_irq); in s3c_irq_unmask()
128 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_ack()
129 unsigned long bitval = 1UL << irq_data->offset; in s3c_irq_ack()
131 writel_relaxed(bitval, intc->reg_pending); in s3c_irq_ack()
132 if (intc->reg_intpnd) in s3c_irq_ack()
133 writel_relaxed(bitval, intc->reg_intpnd); in s3c_irq_ack()
144 irq_set_handler(data->irq, handle_edge_irq); in s3c_irq_type()
148 irq_set_handler(data->irq, handle_level_irq); in s3c_irq_type()
152 return -EINVAL; in s3c_irq_type()
200 return -EINVAL; in s3c_irqext_type_set()
216 if ((data->hwirq >= 4) && (data->hwirq <= 7)) { in s3c_irqext_type()
219 gpcon_offset = (data->hwirq) * 2; in s3c_irqext_type()
220 extint_offset = (data->hwirq) * 4; in s3c_irqext_type()
221 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { in s3c_irqext_type()
224 gpcon_offset = (data->hwirq - 8) * 2; in s3c_irqext_type()
225 extint_offset = (data->hwirq - 8) * 4; in s3c_irqext_type()
226 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { in s3c_irqext_type()
229 gpcon_offset = (data->hwirq - 8) * 2; in s3c_irqext_type()
230 extint_offset = (data->hwirq - 16) * 4; in s3c_irqext_type()
232 return -EINVAL; in s3c_irqext_type()
245 if (data->hwirq <= 3) { in s3c_irqext0_type()
248 gpcon_offset = (data->hwirq) * 2; in s3c_irqext0_type()
249 extint_offset = (data->hwirq) * 4; in s3c_irqext0_type()
251 return -EINVAL; in s3c_irqext0_type()
268 .name = "s3c-level",
276 .name = "s3c-ext",
285 .name = "s3c-ext0",
297 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_demux()
298 struct s3c_irq_intc *sub_intc = irq_data->sub_intc; in s3c_irq_demux()
302 /* we're using individual domains for the non-dt case in s3c_irq_demux()
306 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0; in s3c_irq_demux()
310 src = readl_relaxed(sub_intc->reg_pending); in s3c_irq_demux()
311 msk = readl_relaxed(sub_intc->reg_mask); in s3c_irq_demux()
314 src &= irq_data->sub_bits; in s3c_irq_demux()
319 irq = irq_find_mapping(sub_intc->domain, offset + n); in s3c_irq_demux()
332 pnd = readl_relaxed(intc->reg_intpnd); in s3c24xx_handle_intc()
336 /* non-dt machines use individual domains */ in s3c24xx_handle_intc()
337 if (!irq_domain_get_of_node(intc->domain)) in s3c24xx_handle_intc()
343 * what looks like the logical-or of the two interrupt numbers. in s3c24xx_handle_intc()
347 offset = readl_relaxed(intc->reg_intpnd + 4); in s3c24xx_handle_intc()
356 handle_domain_irq(intc->domain, intc_offset + offset, regs); in s3c24xx_handle_intc()
377 * s3c24xx_set_fiq - set the FIQ routing
395 offs = irq - FIQ_START; in s3c24xx_set_fiq()
417 struct s3c_irq_intc *intc = h->host_data; in s3c24xx_irq_map()
418 struct s3c_irq_data *irq_data = &intc->irqs[hw]; in s3c24xx_irq_map()
424 irq_data->intc = intc; in s3c24xx_irq_map()
425 irq_data->offset = hw; in s3c24xx_irq_map()
427 parent_intc = intc->parent; in s3c24xx_irq_map()
430 switch (irq_data->type) { in s3c24xx_irq_map()
445 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2) in s3c24xx_irq_map()
461 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); in s3c24xx_irq_map()
462 return -EINVAL; in s3c24xx_irq_map()
467 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) { in s3c24xx_irq_map()
468 if (irq_data->parent_irq > 31) { in s3c24xx_irq_map()
469 pr_err("irq-s3c24xx: parent irq %lu is out of range\n", in s3c24xx_irq_map()
470 irq_data->parent_irq); in s3c24xx_irq_map()
471 return -EINVAL; in s3c24xx_irq_map()
474 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c24xx_irq_map()
475 parent_irq_data->sub_intc = intc; in s3c24xx_irq_map()
476 parent_irq_data->sub_bits |= (1UL << hw); in s3c24xx_irq_map()
479 irqno = irq_find_mapping(parent_intc->domain, in s3c24xx_irq_map()
480 irq_data->parent_irq); in s3c24xx_irq_map()
482 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", in s3c24xx_irq_map()
483 irq_data->parent_irq); in s3c24xx_irq_map()
484 return -EINVAL; in s3c24xx_irq_map()
505 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; in s3c24xx_clear_intc()
514 writel_relaxed(pend, intc->reg_pending); in s3c24xx_clear_intc()
515 if (intc->reg_intpnd) in s3c24xx_clear_intc()
516 writel_relaxed(pend, intc->reg_intpnd); in s3c24xx_clear_intc()
536 return ERR_PTR(-ENOMEM); in s3c24xx_init_intc()
538 intc->irqs = irq_data; in s3c24xx_init_intc()
541 intc->parent = parent; in s3c24xx_init_intc()
550 intc->reg_pending = base; in s3c24xx_init_intc()
551 intc->reg_mask = base + 0x08; in s3c24xx_init_intc()
552 intc->reg_intpnd = base + 0x10; in s3c24xx_init_intc()
558 intc->reg_pending = base + 0x18; in s3c24xx_init_intc()
559 intc->reg_mask = base + 0x1c; in s3c24xx_init_intc()
565 intc->reg_pending = base + 0x40; in s3c24xx_init_intc()
566 intc->reg_mask = base + 0x48; in s3c24xx_init_intc()
567 intc->reg_intpnd = base + 0x50; in s3c24xx_init_intc()
575 intc->reg_mask = base + 0xa4; in s3c24xx_init_intc()
576 intc->reg_pending = base + 0xa8; in s3c24xx_init_intc()
582 ret = -EINVAL; in s3c24xx_init_intc()
586 /* now that all the data is complete, init the irq-domain */ in s3c24xx_init_intc()
588 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, in s3c24xx_init_intc()
591 if (!intc->domain) { in s3c24xx_init_intc()
592 pr_err("irq: could not create irq-domain\n"); in s3c24xx_init_intc()
593 ret = -EINVAL; in s3c24xx_init_intc()
607 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
608 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
609 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
610 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
641 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
659 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
670 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
710 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
728 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
766 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
767 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
769 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
770 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
812 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
825 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
841 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
842 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
843 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
852 { .type = S3C_IRQTYPE_NONE }, /* reserved */
853 { .type = S3C_IRQTYPE_NONE }, /* reserved */
854 { .type = S3C_IRQTYPE_NONE }, /* reserved */
855 { .type = S3C_IRQTYPE_NONE }, /* reserved */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
874 { .type = S3C_IRQTYPE_NONE }, /* reserved */
875 { .type = S3C_IRQTYPE_NONE }, /* reserved */
876 { .type = S3C_IRQTYPE_NONE }, /* reserved */
878 { .type = S3C_IRQTYPE_NONE }, /* reserved */
944 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
945 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
946 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
947 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
948 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
949 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
950 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
952 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1019 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1020 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1021 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1022 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1025 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1093 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1094 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1106 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1152 struct s3c_irq_intc *parent_intc = intc->parent; in s3c24xx_irq_map_of()
1153 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw]; in s3c24xx_irq_map_of()
1156 irq_data->intc = intc; in s3c24xx_irq_map_of()
1157 irq_data->offset = intc_hw; in s3c24xx_irq_map_of()
1184 return -EINVAL; in s3c24xx_irq_xlate_of()
1188 return -EINVAL; in s3c24xx_irq_xlate_of()
1195 parent_intc = intc->parent; in s3c24xx_irq_xlate_of()
1197 irq_data = &intc->irqs[intspec[2]]; in s3c24xx_irq_xlate_of()
1198 irq_data->parent_irq = intspec[1]; in s3c24xx_irq_xlate_of()
1199 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c24xx_irq_xlate_of()
1200 parent_irq_data->sub_intc = intc; in s3c24xx_irq_xlate_of()
1201 parent_irq_data->sub_bits |= (1UL << intspec[2]); in s3c24xx_irq_xlate_of()
1204 irqno = irq_create_mapping(parent_intc->domain, intspec[1]); in s3c24xx_irq_xlate_of()
1241 pr_err("irq-s3c24xx: could not map irq registers\n"); in s3c_init_intc_of()
1242 return -EINVAL; in s3c_init_intc_of()
1248 pr_err("irq: could not create irq-domain\n"); in s3c_init_intc_of()
1249 return -EINVAL; in s3c_init_intc_of()
1255 pr_debug("irq: found controller %s\n", ctrl->name); in s3c_init_intc_of()
1259 return -ENOMEM; in s3c_init_intc_of()
1261 intc->domain = domain; in s3c_init_intc_of()
1262 intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data), in s3c_init_intc_of()
1264 if (!intc->irqs) { in s3c_init_intc_of()
1266 return -ENOMEM; in s3c_init_intc_of()
1269 if (ctrl->parent) { in s3c_init_intc_of()
1270 intc->reg_pending = reg_base + ctrl->offset; in s3c_init_intc_of()
1271 intc->reg_mask = reg_base + ctrl->offset + 0x4; in s3c_init_intc_of()
1273 if (*(ctrl->parent)) { in s3c_init_intc_of()
1274 intc->parent = *(ctrl->parent); in s3c_init_intc_of()
1277 ctrl->name); in s3c_init_intc_of()
1278 kfree(intc->irqs); in s3c_init_intc_of()
1283 intc->reg_pending = reg_base + ctrl->offset; in s3c_init_intc_of()
1284 intc->reg_mask = reg_base + ctrl->offset + 0x08; in s3c_init_intc_of()
1285 intc->reg_intpnd = reg_base + ctrl->offset + 0x10; in s3c_init_intc_of()
1314 IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1336 IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);