Lines Matching +full:deep +full:- +full:touch

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
30 #define PWER		__REG(0x40F50010)	/* Power Manager Wake-up Enable Register */
31 #define PWSR		__REG(0x40F50014)	/* Power Manager Wake-up Status Register */
33 #define DCDCSR		__REG(0x40F50080)	/* DC-DC Controller Status Register */
42 #define AD3ER		__REG(0x40f40008)	/* Application Subsystem Wake-Up from D3 Enable */
43 #define AD3SR		__REG(0x40f4000c)	/* Application Subsystem Wake-Up from D3 Status */
44 #define AD2D0ER		__REG(0x40f40010)	/* Application Subsystem Wake-Up from D2 to D0 Enable */
45 #define AD2D0SR		__REG(0x40f40014)	/* Application Subsystem Wake-Up from D2 to D0 Status */
46 #define AD2D1ER		__REG(0x40f40018)	/* Application Subsystem Wake-Up from D2 to D1 Enable */
47 #define AD2D1SR		__REG(0x40f4001c)	/* Application Subsystem Wake-Up from D2 to D1 Status */
48 #define AD1D0ER		__REG(0x40f40020)	/* Application Subsystem Wake-Up from D1 to D0 Enable */
49 #define AD1D0SR		__REG(0x40f40024)	/* Application Subsystem Wake-Up from D1 to D0 Status */
72  * Application Subsystem Wake-Up bits.
104  * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
117 #define PXA3xx_PM_S3D4C4	0x07	/* aka deep sleep */
143 #define ACCR_HSS_MASK		(0x3 << 14)	/* System Bus-Clock Frequency Select */
145 #define ACCR_XN_MASK		(0x7 << 8)	/* Core PLL Turbo-Mode-to-Run-Mode Ratio */
146 #define ACCR_XL_MASK		(0x1f)		/* Core PLL Run-Mode-to-Oscillator Ratio */
180 #define CKEN_TOUCH	25	/* < Touch screen Interface Clock Enable */
191 #define CKEN_1WIRE	40	/* < 1-wire clock enable */
193 #define CKEN_MINI_IM	48	/* < Mini-IM */