Lines Matching +full:opp +full:- +full:266000000
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
6 * Copyright (C) 2004-2009 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
25 * OPP API exists, the data in this file should be converted to use it.
34 * struct prcm_config - define clock rates on a per-OPP basis (24xx)
40 * This is deprecated. As soon as we have a decent OPP API, we should
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
64 /*-------------------------------------------------------------------------
66 *-------------------------------------------------------------------------*/
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
85 /* 2430-Ratio Config 2 */
102 /* 2430-Ratio Bootm (BYPASS) */
123 /* 2420-PRCM III 532MHz core */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
144 /* 2420-PRCM II 600MHz core */
154 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
155 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
157 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
165 /* 2420-PRCM I 660MHz core */
175 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
176 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
178 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
186 /* 2420-PRCM VII (boot) */
215 /*-------------------------------------------------------------------------
219 *-------------------------------------------------------------------------*/
229 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
313 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
344 * 2430 - chassis (sedna)
361 * 2420 Equivalent - mode registers
407 #define S266M 266000000