Lines Matching full:mhz
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
145 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
146 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
147 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
152 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
154 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
155 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
157 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
162 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
165 /* 2420-PRCM I 660MHz core */
166 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
167 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
168 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
173 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
175 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
176 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
178 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
183 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
313 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
315 /* Core frequency changed from 330/165 to 329/164 MHz*/
353 /* PRCM I target DPLL = 2*330MHz = 660MHz */
362 * PRCM II , target DPLL = 2*300MHz = 600MHz
375 /* PRCM III target DPLL = 2*266 = 532MHz*/