Lines Matching +full:1 +full:mhz
20 * 2430 (iva2.1, NOdsp, mdm)
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
48 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
103 #define RB_CLKSEL_L3 (1 << 0)
104 #define RB_CLKSEL_L4 (1 << 5)
105 #define RB_CLKSEL_USB (1 << 25)
109 #define RB_CLKSEL_MPU (1 << 0)
111 #define RB_CLKSEL_DSP (1 << 0)
112 #define RB_CLKSEL_DSP_IF (1 << 5)
114 #define RB_CLKSEL_GFX (1 << 0)
116 #define RB_CLKSEL_MDM (1 << 0)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
135 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
137 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
145 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
146 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
147 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
152 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
154 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
155 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
157 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
162 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
165 /* 2420-PRCM I 660MHz core */
166 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
167 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
168 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
173 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
175 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
176 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
177 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
178 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
183 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
187 #define RVII_CLKSEL_L3 (1 << 0)
188 #define RVII_CLKSEL_L4 (1 << 5)
189 #define RVII_CLKSEL_DSS1 (1 << 8)
191 #define RVII_CLKSEL_VLYNQ (1 << 15)
192 #define RVII_CLKSEL_SSI (1 << 20)
193 #define RVII_CLKSEL_USB (1 << 25)
200 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
203 #define RVII_CLKSEL_DSP (1 << 0)
204 #define RVII_CLKSEL_DSP_IF (1 << 5)
206 #define RVII_CLKSEL_IVA (1 << 8)
212 #define RVII_CLKSEL_GFX (1 << 0)
229 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
289 #define M3_DPLL_DIV_12 (1 << 8)
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
308 #define M2_DPLL_DIV_12 (1 << 8)
313 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
315 /* Core frequency changed from 330/165 to 329/164 MHz*/
329 #define MB_DPLL_MULT (1 << 12)
353 /* PRCM I target DPLL = 2*330MHz = 660MHz */
355 #define MI_DPLL_DIV_12 (1 << 8)
362 * PRCM II , target DPLL = 2*300MHz = 600MHz
365 #define MII_DPLL_DIV_12 (1 << 8)
375 /* PRCM III target DPLL = 2*266 = 532MHz*/
393 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)