Lines Matching refs:ck_dpll1
81 static struct clk ck_dpll1 = { variable
95 .parent = &ck_dpll1,
119 .parent = &ck_dpll1,
130 .parent = &ck_dpll1,
149 .parent = &ck_dpll1,
211 .parent = &ck_dpll1,
223 .parent = &ck_dpll1,
233 .parent = &ck_dpll1,
264 .parent = &ck_dpll1,
384 .parent = &ck_dpll1,
397 .parent = &ck_dpll1,
673 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
757 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, in omap1_show_rates()
834 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ in omap1_clk_init()
838 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; in omap1_clk_init()
839 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; in omap1_clk_init()
846 ck_dpll1.rate /= 2; in omap1_clk_init()
849 ck_dpll1.rate /= 4; in omap1_clk_init()
854 propagate_rate(&ck_dpll1); in omap1_clk_init()
907 unsigned long rate = ck_dpll1.rate; in omap1_clk_late_init()
916 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; in omap1_clk_late_init()
918 propagate_rate(&ck_dpll1); in omap1_clk_late_init()
920 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate); in omap1_clk_late_init()