43 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;  variable
52 	__raw_writel(1, mmp_timer_base + TMR_CVWR(1));  in timer_read()
57 	return __raw_readl(mmp_timer_base + TMR_CVWR(1));  in timer_read()
72 	__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));  in timer_interrupt()
77 	__raw_writel(0x02, mmp_timer_base + TMR_CER);  in timer_interrupt()
94 	__raw_writel(0x02, mmp_timer_base + TMR_CER);  in timer_set_next_event()
99 	__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));  in timer_set_next_event()
100 	__raw_writel(0x01, mmp_timer_base + TMR_IER(0));  in timer_set_next_event()
105 	__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));  in timer_set_next_event()
110 	__raw_writel(0x03, mmp_timer_base + TMR_CER);  in timer_set_next_event()
123 	__raw_writel(0x00, mmp_timer_base + TMR_IER(0));  in timer_set_shutdown()
153 	uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);  in timer_config()
155 	__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */  in timer_config()
160 	__raw_writel(ccr, mmp_timer_base + TMR_CCR);  in timer_config()
163 	__raw_writel(0x2, mmp_timer_base + TMR_CMR);  in timer_config()
165 	__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */  in timer_config()
166 	__raw_writel(0x7, mmp_timer_base + TMR_ICR(0));  /* clear status */  in timer_config()
167 	__raw_writel(0x0, mmp_timer_base + TMR_IER(0));  in timer_config()
169 	__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */  in timer_config()
170 	__raw_writel(0x7, mmp_timer_base + TMR_ICR(1));  /* clear status */  in timer_config()
171 	__raw_writel(0x0, mmp_timer_base + TMR_IER(1));  in timer_config()
174 	__raw_writel(0x2, mmp_timer_base + TMR_CER);  in timer_config()
215 	mmp_timer_base = of_iomap(np, 0);  in mmp_dt_init_timer()
216 	if (!mmp_timer_base)  in mmp_dt_init_timer()