Lines Matching +full:0 +full:x11000
23 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
25 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
27 * 0x50000000 0x10000000 ioremap'd EXP BUS
29 * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
31 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG
33 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG
35 * 0x60000000 0x00004000 0xFEF15000 QMgr
41 #define IXP4XX_QMGR_BASE_PHYS 0x60000000
47 #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
48 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
49 #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
54 #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
55 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)
56 #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
61 #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
62 #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000
63 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
65 #define IXP4XX_EXP_CS0_OFFSET 0x00
66 #define IXP4XX_EXP_CS1_OFFSET 0x04
67 #define IXP4XX_EXP_CS2_OFFSET 0x08
68 #define IXP4XX_EXP_CS3_OFFSET 0x0C
69 #define IXP4XX_EXP_CS4_OFFSET 0x10
70 #define IXP4XX_EXP_CS5_OFFSET 0x14
71 #define IXP4XX_EXP_CS6_OFFSET 0x18
72 #define IXP4XX_EXP_CS7_OFFSET 0x1C
73 #define IXP4XX_EXP_CFG0_OFFSET 0x20
74 #define IXP4XX_EXP_CFG1_OFFSET 0x24
75 #define IXP4XX_EXP_CFG2_OFFSET 0x28
76 #define IXP4XX_EXP_CFG3_OFFSET 0x2C
101 #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
102 #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
103 #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
104 #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
105 #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
106 #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
107 #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
108 #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
109 #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
110 #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
111 #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
112 #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
114 #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
115 #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
116 #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
117 #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
118 #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
119 #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
120 #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
123 #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
124 #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
125 #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
126 #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
127 #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
128 #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
129 #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
130 #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
131 #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
133 #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
134 #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
135 #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
136 #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
137 #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
138 #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
139 #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
144 #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
145 #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
146 #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
147 #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
148 #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
149 #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
150 #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
151 #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
152 #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
173 #define IXP4XX_OST_ENABLE 0x00000001
174 #define IXP4XX_OST_ONE_SHOT 0x00000002
176 #define IXP4XX_OST_RELOAD_MASK 0x00000003
177 #define IXP4XX_OST_DISABLED 0x00000000
178 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001
179 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002
180 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
181 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
182 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
184 #define IXP4XX_WDT_KEY 0x0000482E
186 #define IXP4XX_WDT_RESET_ENABLE 0x00000001
187 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002
188 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004
194 #define PCI_NP_AD_OFFSET 0x00
195 #define PCI_NP_CBE_OFFSET 0x04
196 #define PCI_NP_WDATA_OFFSET 0x08
197 #define PCI_NP_RDATA_OFFSET 0x0c
198 #define PCI_CRP_AD_CBE_OFFSET 0x10
199 #define PCI_CRP_WDATA_OFFSET 0x14
200 #define PCI_CRP_RDATA_OFFSET 0x18
201 #define PCI_CSR_OFFSET 0x1c
202 #define PCI_ISR_OFFSET 0x20
203 #define PCI_INTEN_OFFSET 0x24
204 #define PCI_DMACTRL_OFFSET 0x28
205 #define PCI_AHBMEMBASE_OFFSET 0x2c
206 #define PCI_AHBIOBASE_OFFSET 0x30
207 #define PCI_PCIMEMBASE_OFFSET 0x34
208 #define PCI_AHBDOORBELL_OFFSET 0x38
209 #define PCI_PCIDOORBELL_OFFSET 0x3C
210 #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
211 #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
212 #define PCI_ATPDMA0_LENADDR_OFFSET 0x48
213 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
214 #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
215 #define PCI_ATPDMA1_LENADDR_OFFSET 0x54
250 #define PCI_CSR_HOST 0x00000001
251 #define PCI_CSR_ARBEN 0x00000002
252 #define PCI_CSR_ADS 0x00000004
253 #define PCI_CSR_PDS 0x00000008
254 #define PCI_CSR_ABE 0x00000010
255 #define PCI_CSR_DBT 0x00000020
256 #define PCI_CSR_ASE 0x00000100
257 #define PCI_CSR_IC 0x00008000
260 #define PCI_ISR_PSE 0x00000001
261 #define PCI_ISR_PFE 0x00000002
262 #define PCI_ISR_PPE 0x00000004
263 #define PCI_ISR_AHBE 0x00000008
264 #define PCI_ISR_APDC 0x00000010
265 #define PCI_ISR_PADC 0x00000020
266 #define PCI_ISR_ADB 0x00000040
267 #define PCI_ISR_PDB 0x00000080
270 #define PCI_INTEN_PSE 0x00000001
271 #define PCI_INTEN_PFE 0x00000002
272 #define PCI_INTEN_PPE 0x00000004
273 #define PCI_INTEN_AHBE 0x00000008
274 #define PCI_INTEN_APDC 0x00000010
275 #define PCI_INTEN_PADC 0x00000020
276 #define PCI_INTEN_ADB 0x00000040
277 #define PCI_INTEN_PDB 0x00000080
287 #define NP_CMD_IOREAD 0x2
288 #define NP_CMD_IOWRITE 0x3
289 #define NP_CMD_CONFIGREAD 0xa
290 #define NP_CMD_CONFIGWRITE 0xb
291 #define NP_CMD_MEMREAD 0x6
292 #define NP_CMD_MEMWRITE 0x7
298 #define CRP_AD_CBE_WRITE 0x00010000
300 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
304 #define IXP4XX_FEATURE_RCOMP (1 << 0)