22 	phy_write(dev, 0x1d, 0x1f);  in ar8031_phy_fixup()
23 	phy_write(dev, 0x1e, 0x8);  in ar8031_phy_fixup()
26 	phy_write(dev, 0xd, 0x3);  in ar8031_phy_fixup()
27 	phy_write(dev, 0xe, 0x805d);  in ar8031_phy_fixup()
28 	phy_write(dev, 0xd, 0x4003);  in ar8031_phy_fixup()
29 	val = phy_read(dev, 0xe);  in ar8031_phy_fixup()
30 	val &= ~(0x1 << 8);  in ar8031_phy_fixup()
31 	phy_write(dev, 0xe, val);  in ar8031_phy_fixup()
33 	return 0;  in ar8031_phy_fixup()
39 	phy_write(dev, 0x1e, 0x21);  in bcm54220_phy_fixup()
40 	phy_write(dev, 0x1f, 0x7ea8);  in bcm54220_phy_fixup()
41 	phy_write(dev, 0x1e, 0x2f);  in bcm54220_phy_fixup()
42 	phy_write(dev, 0x1f, 0x71b7);  in bcm54220_phy_fixup()
44 	return 0;  in bcm54220_phy_fixup()
47 #define PHY_ID_AR8031	0x004dd074
48 #define PHY_ID_BCM54220	0x600d8589
53 		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,  in imx7d_enet_phy_init()
55 		phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,  in imx7d_enet_phy_init()
66 		regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);  in imx7d_enet_clk_sel()
67 		regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);  in imx7d_enet_clk_sel()
88 		platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);  in imx7d_init_late()