Lines Matching +full:0 +full:xfb000000

13  * 0xff800000	0x40000000	1MB	X-Bus
14  * 0xff000000	0x7c000000	1MB	PCI I/O space
15  * 0xfe000000	0x42000000	1MB	CSR
16  * 0xfd000000	0x78000000	1MB	Outbound write flush (not supported)
17  * 0xfc000000	0x79000000	1MB	PCI IACK/special space
18  * 0xfb000000	0x7a000000	16MB	PCI Config type 1
19  * 0xfa000000	0x7b000000	16MB	PCI Config type 0
20  * 0xf9000000	0x50000000	1MB	Cache flush
21  * 0xf0000000	0x80000000	16MB	ISA memory
30 #define XBUS_SIZE		0x00100000
31 #define XBUS_BASE		MMU_IO(0xff800000, 0x40000000)
33 #define ARMCSR_SIZE		0x00100000
34 #define ARMCSR_BASE		MMU_IO(0xfe000000, 0x42000000)
36 #define WFLUSH_SIZE		0x00100000
37 #define WFLUSH_BASE		MMU_IO(0xfd000000, 0x78000000)
39 #define PCIIACK_SIZE		0x00100000
40 #define PCIIACK_BASE		MMU_IO(0xfc000000, 0x79000000)
42 #define PCICFG1_SIZE		0x01000000
43 #define PCICFG1_BASE		MMU_IO(0xfb000000, 0x7a000000)
45 #define PCICFG0_SIZE		0x01000000
46 #define PCICFG0_BASE		MMU_IO(0xfa000000, 0x7b000000)
48 #define PCIMEM_SIZE		0x01000000
49 #define PCIMEM_BASE		MMU_IO(0xf0000000, 0x80000000)
51 #define XBUS_CS2		0x40012000
53 #define XBUS_SWITCH		((volatile unsigned char *)(XBUS_BASE + 0x12000))
59 #define UNCACHEABLE_ADDR	(ARMCSR_BASE + 0x108)	/* CSR_ROMBASEMASK */
63 #define PIC_LO			0x20
64 #define PIC_MASK_LO		0x21
65 #define PIC_HI			0xA0
66 #define PIC_MASK_HI		0xA1
69 #define GPIO_CCLK		0x800
70 #define GPIO_DSCLK		0x400
71 #define GPIO_E2CLK		0x200
72 #define GPIO_IOLOAD		0x100
73 #define GPIO_RED_LED		0x080
74 #define GPIO_WDTIMER		0x040
75 #define GPIO_DATA		0x020
76 #define GPIO_IOCLK		0x010
77 #define GPIO_DONE		0x008
78 #define GPIO_FAN		0x004
79 #define GPIO_GREEN_LED		0x002
80 #define GPIO_RESET		0x001