Lines Matching +full:0 +full:x01c70000
41 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
42 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
43 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
54 .start = 0x01c66000,
55 .end = 0x01c667ff,
73 .id = 0,
90 if (chipselect_mask & BIT(0)) in dm355_init_spi0()
102 #define INTMUX 0x18
103 #define EVTMUX 0x1c
113 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
125 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
132 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
133 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
140 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
141 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
142 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
145 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
146 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
147 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
148 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
150 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
151 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
152 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
153 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
154 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
155 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
156 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
229 {0, 3},
235 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
236 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
237 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
238 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
239 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
240 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
241 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
242 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
243 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
244 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
245 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
246 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
247 { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
248 { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
261 .start = 0x01c00000,
262 .end = 0x01c00000 + SZ_64K - 1,
267 .start = 0x01c10000,
268 .end = 0x01c10000 + SZ_1K - 1,
273 .start = 0x01c10400,
274 .end = 0x01c10400 + SZ_1K - 1,
292 .id = 0,
341 .start = 0x01c70800,
342 .end = 0x01c70800 + 0xff,
348 .start = 0x01c70000,
349 .end = 0x01c70000 + 0xf,
380 .start = 0x01c70600,
381 .end = 0x01c70600 + 0x1ff,
410 .end = DM355_OSD_BASE + 0x17f,
435 .end = DM355_VENC_BASE + 0x17f,
455 .end = DM355_VENC_BASE + 0x17f,
479 return 0; in dm355_vpbe_setup_pinmux()
506 return 0; in dm355_venc_setup_clock()
591 .base = 0,
615 .variant = 0x0,
616 .part_no = 0xb73b,
617 .manufacturer = 0x00f,
645 .flags = 0,
658 .flags = 0,
671 .flags = 0,
704 .jtag_id_reg = 0x01c40028,
710 .sram_dma = 0x00010000,
738 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ); in dm355_init_time()
797 return 0; in dm355_init_video()
818 int ret = 0; in dm355_init_devices()
821 return 0; in dm355_init_devices()