1 // SPDX-License-Identifier: GPL-2.0-only
3  * PCI-E support for CNS3xxx
38 	return root->private_data;  in sysdata_to_cnspci()
43 	return sysdata_to_cnspci(dev->sysdata);  in pdev_to_cnspci()
48 	return sysdata_to_cnspci(bus->sysdata);  in pbus_to_cnspci()
55 	int busno = bus->number;  in cns3xxx_pci_map_bus()
60 	if (!cnspci->linked && busno > 0)  in cns3xxx_pci_map_bus()
71 			base = cnspci->host_regs;  in cns3xxx_pci_map_bus()
77 			base = cnspci->cfg0_regs;  in cns3xxx_pci_map_bus()
81 		base = cnspci->cfg1_regs + ((busno & 0xf) << 20);  in cns3xxx_pci_map_bus()
90 	u32 mask = (0x1ull << (size * 8)) - 1;  in cns3xxx_pci_read_config()
95 	if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&  in cns3xxx_pci_read_config()
110 	struct resource *res_io = &cnspci->res_io;  in cns3xxx_pci_setup()
111 	struct resource *res_mem = &cnspci->res_mem;  in cns3xxx_pci_setup()
116 	pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);  in cns3xxx_pci_setup()
117 	pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);  in cns3xxx_pci_setup()
131 	int irq = cnspci->irqs[!!dev->bus->number];  in cns3xxx_pcie_map_irq()
134 		pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),  in cns3xxx_pcie_map_irq()
135 		PCI_FUNC(dev->devfn), slot, pin, irq);  in cns3xxx_pcie_map_irq()
148 			.end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
152 			.name = "PCIe0 non-prefetchable",
154 			.end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
167 			.end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
171 			.name = "PCIe1 non-prefetchable",
173 			.end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
183 	int port = cnspci->port;  in cns3xxx_pcie_check_link()
203 			cnspci->linked = 1;  in cns3xxx_pcie_check_link()
215 	void __iomem *base = cnspci->host_regs + (where & 0xffc);  in cns3xxx_write_config()
217 	u32 mask = (0x1ull << (size * 8)) - 1;  in cns3xxx_write_config()
231 	u16 mem_base  = cnspci->res_mem.start >> 16;  in cns3xxx_pcie_hw_init()
232 	u16 mem_limit = cnspci->res_mem.end   >> 16;  in cns3xxx_pcie_hw_init()
233 	u16 io_base   = cnspci->res_io.start  >> 16;  in cns3xxx_pcie_hw_init()
234 	u16 io_limit  = cnspci->res_io.end    >> 16;  in cns3xxx_pcie_hw_init()
244 	if (!cnspci->linked)  in cns3xxx_pcie_hw_init()
251 	__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));  in cns3xxx_pcie_hw_init()
258 		regs->ARM_pc += 4;  in cns3xxx_pcie_abort_handler()