Lines Matching +full:0 +full:x41000000
31 * the least significant 16 bits to be 0x8000, but we could probably
32 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
35 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
36 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
41 #define PG_DIR_SIZE 0x5000
44 #define PG_DIR_SIZE 0x4000
61 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
65 * 0xc0008000, you call this at __pa(0xc0008000).
91 mrc p15, 0, r9, c0, c0 @ get processor id
93 movs r10, r5 @ invalid processor (r5=0)?
98 mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
99 and r3, r3, #0xf @ extract VMSA support
150 mov r5, #0 @ high TTBR0
184 mov r3, #0
199 add r3, r4, #0x1000 @ first PMD table address
211 add r3, r3, #0x1000 @ next PMD table
215 add r4, r4, #0x1000 @ point to the PMD tables
261 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
262 str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
331 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
332 orr r3, r7, #0x7c000000
337 * Map in screen at 0x02000000 & SCREEN2_BASE
341 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
342 orr r3, r7, #0x02000000
344 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
349 sub r4, r4, #0x1000 @ point to the PGD table
384 mrc p15, 0, r9, c0, c0 @ get processor id
398 ldrd r4, r5, [r3, #0] @ get secondary_data.pgdir
417 mov fp, #0
462 mcrr p15, 0, r4, r5, c2 @ load TTBR0
465 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
466 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
490 mcr p15, 0, r0, c1, c0, 0 @ write control reg
491 mrc p15, 0, r3, c0, c0, 0 @ read id reg
504 and r3, r9, #0x000f0000 @ architecture version
505 teq r3, #0x000f0000 @ CPU ID supported?
508 bic r3, r9, #0x00ff0000
509 bic r3, r3, #0x0000000f @ mask 0xff00fff0
510 mov r4, #0x41000000
511 orr r4, r4, #0x0000b000
512 orr r4, r4, #0x00000020 @ val 0x4100b020
516 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
517 and r0, r0, #0xc0000000 @ multiprocessing extensions and
518 teq r0, #0x80000000 @ not part of a uniprocessor system?
523 mov r4, #0x41000000
524 orr r4, r4, #0x0000c000
525 orr r4, r4, #0x00000090
529 @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
533 teq r0, #0x0 @ '0' on actual UP A9 hardware
537 and r0, r0, #0x3 @ number of CPUs
538 teq r0, #0x0 @ is 1?
560 ALT_UP(.long 0)
584 mov r3, #0
590 #define LOW_OFFSET 0x4
591 #define HIGH_OFFSET 0x0
593 #define LOW_OFFSET 0x0
594 #define HIGH_OFFSET 0x4
608 mvn ip, #0
642 moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
648 bic r6, #0x0080
650 orrcs r6, #0x0080
652 orr r6, #0x4000
657 tst ip, #0x4000
658 and ip, #0x8f00
660 orreq ip, r0 @ mask in offset bits 7-0
666 bic ip, #0x20
676 moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
678 moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
684 bic ip, ip, #0xff000000
685 tst ip, #0x000f0000 @ check the rotation field
687 biceq ip, ip, #0x00004000 @ clear bit 22
688 orreq ip, ip, r0 @ mask in offset bits 7-0
690 bic ip, ip, #0x000000ff
691 tst ip, #0xf00 @ check the rotation field
693 biceq ip, ip, #0x400000 @ clear bit 22
694 orreq ip, ip, r0 @ mask in offset bits 7-0
709 mov r3, #0 @ no offset
721 .word 0
727 .quad 0