Lines Matching +full:armv6 +full:- +full:capable
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-armv.S
6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
9 * Low-level vector interface routines
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
23 #include <mach/entry-macro.S>
30 #include <asm/uaccess-asm.h>
32 #include "entry-header.S"
33 #include <asm/entry-macro-multi.S>
65 @ Call the processor-specific abort handler:
67 @ r2 - pt_regs
68 @ r4 - aborted context pc
69 @ r5 - aborted context psr
90 ARM( stmib sp, {r1 - lr} )
91 THUMB( stmia sp, {r0 - r12} )
120 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
125 ldmia r0, {r4 - r6}
127 mov r7, #-1 @ "" "" "" ""
129 stmia r0, {r5 - r7} @ lr_<exception>,
148 UNWIND(.save {r0 - pc} )
149 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
159 stmia sp, {r1 - r12}
161 ldmia r0, {r3 - r5}
162 add r7, sp, #S_SP - 4 @ here for interlock avoidance
163 mov r6, #-1 @ "" "" "" ""
164 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
166 str r3, [sp, #-4]! @ save the "real" r0 copied
174 @ r2 - sp_svc
175 @ r3 - lr_svc
176 @ r4 - lr_<exception>, already fixed up for correct return/restart
177 @ r5 - spsr_<exception>
178 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
180 stmia r7, {r2 - r6}
260 @ r0 - instruction
263 ldr r0, [r4, #-4]
266 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
267 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
339 stmfd sp!, {r1 - r2}
344 ldmfd sp!, {r1 - r2}
361 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
372 ARM( stmib sp, {r1 - r12} )
373 THUMB( stmia sp, {r0 - r12} )
378 ldmia r0, {r3 - r5}
380 mov r6, #-1 @ "" "" "" ""
390 @ r4 - lr_<exception>, already fixed up for correct return/restart
391 @ r5 - spsr_<exception>
392 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
396 stmia r0, {r4 - r6}
398 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
466 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
468 @ r3 = regs->ARM_cpsr
483 sub r4, r2, #4 @ ARM instr at LR - 4
489 @ r0 = 32-bit ARM instruction which caused the exception
490 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
492 @ lr = 32-bit undefined instruction function
498 sub r4, r2, #2 @ First half of thumb instr at LR - 2
501 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
507 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
531 @ r0 = the two 16-bit Thumb instructions which caused the exception
532 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
533 @ r4 = PC value for the first 16-bit Thumb instruction
541 .arch armv6
567 * Check whether the instruction is a co-processor instruction.
568 * If yes, we need to call the relevant co-processor handler.
570 * Note that we don't do a full check here for the co-processor
573 * co-processor instructions. However, we have to watch out
577 * NEON instructions are co-processor instructions, so we have
584 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
592 @ Fall-through from Thumb-2 __und_usr
617 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
772 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
773 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
805 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
806 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
817 * Each segment is 32-byte aligned and will be moved to the top of the high
835 .if (. - \sym) & 3
836 .rept 4 - (. - \sym) & 3
840 .rept (\size - (. - \sym)) / 4
902 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
904 rsbscs r8, r8, #(2b - 1b)
914 mov r0, #-1
960 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
962 rsbscs r8, r8, #(2b - 1b)
969 mov r0, #-1
983 /* beware -- each __kuser slot must be 8 instructions max */
992 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1001 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1020 * SP points to a minimal amount of processor-private memory, the address
1167 *-----------------------------------------------------------------------------
1169 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1177 *-----------------------------------------------------------------------------