Lines Matching +full:0 +full:x740

13 #define L2X0_CACHE_ID			0x000
14 #define L2X0_CACHE_TYPE			0x004
15 #define L2X0_CTRL			0x100
16 #define L2X0_AUX_CTRL			0x104
17 #define L310_TAG_LATENCY_CTRL		0x108
18 #define L310_DATA_LATENCY_CTRL		0x10C
19 #define L2X0_EVENT_CNT_CTRL		0x200
20 #define L2X0_EVENT_CNT1_CFG		0x204
21 #define L2X0_EVENT_CNT0_CFG		0x208
22 #define L2X0_EVENT_CNT1_VAL		0x20C
23 #define L2X0_EVENT_CNT0_VAL		0x210
24 #define L2X0_INTR_MASK			0x214
25 #define L2X0_MASKED_INTR_STAT		0x218
26 #define L2X0_RAW_INTR_STAT		0x21C
27 #define L2X0_INTR_CLEAR			0x220
28 #define L2X0_CACHE_SYNC			0x730
29 #define L2X0_DUMMY_REG			0x740
30 #define L2X0_INV_LINE_PA		0x770
31 #define L2X0_INV_WAY			0x77C
32 #define L2X0_CLEAN_LINE_PA		0x7B0
33 #define L2X0_CLEAN_LINE_IDX		0x7B8
34 #define L2X0_CLEAN_WAY			0x7BC
35 #define L2X0_CLEAN_INV_LINE_PA		0x7F0
36 #define L2X0_CLEAN_INV_LINE_IDX		0x7F8
37 #define L2X0_CLEAN_INV_WAY		0x7FC
40  * D and one I lockdown register at 0x0900 and 0x0904.
42 #define L2X0_LOCKDOWN_WAY_D_BASE	0x900
43 #define L2X0_LOCKDOWN_WAY_I_BASE	0x904
44 #define L2X0_LOCKDOWN_STRIDE		0x08
45 #define L310_ADDR_FILTER_START		0xC00
46 #define L310_ADDR_FILTER_END		0xC04
47 #define L2X0_TEST_OPERATION		0xF00
48 #define L2X0_LINE_DATA			0xF10
49 #define L2X0_LINE_TAG			0xF30
50 #define L2X0_DEBUG_CTRL			0xF40
51 #define L310_PREFETCH_CTRL		0xF60
52 #define L310_POWER_CTRL			0xF80
54 #define   L310_STNDBY_MODE_EN		(1 << 0)
57 #define L2X0_CACHE_ID_PART_MASK		(0xf << 6)
61 #define L2X0_CACHE_ID_RTL_MASK          0x3f
62 #define L210_CACHE_ID_RTL_R0P2_02	0x00
63 #define L210_CACHE_ID_RTL_R0P1		0x01
64 #define L210_CACHE_ID_RTL_R0P2_01	0x02
65 #define L210_CACHE_ID_RTL_R0P3		0x03
66 #define L210_CACHE_ID_RTL_R0P4		0x0b
67 #define L210_CACHE_ID_RTL_R0P5		0x0f
68 #define L220_CACHE_ID_RTL_R1P7_01REL0	0x06
69 #define L310_CACHE_ID_RTL_R0P0		0x00
70 #define L310_CACHE_ID_RTL_R1P0		0x02
71 #define L310_CACHE_ID_RTL_R2P0		0x04
72 #define L310_CACHE_ID_RTL_R3P0		0x05
73 #define L310_CACHE_ID_RTL_R3P1		0x06
74 #define L310_CACHE_ID_RTL_R3P1_50REL0	0x07
75 #define L310_CACHE_ID_RTL_R3P2		0x08
76 #define L310_CACHE_ID_RTL_R3P3		0x09
78 #define L2X0_EVENT_CNT_CTRL_ENABLE	BIT(0)
81 #define L2X0_EVENT_CNT_CFG_SRC_MASK	0xf
82 #define L2X0_EVENT_CNT_CFG_SRC_DISABLED	0
83 #define L2X0_EVENT_CNT_CFG_INT_DISABLED	0
95 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT	0
96 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK	(7 << 0)
116 #define L310_AUX_CTRL_FULL_LINE_ZERO		BIT(0)	/* R2P0+ */
130 #define L310_LATENCY_CTRL_SETUP(n)		((n) << 0)
136 #define L310_PREFETCH_CTRL_OFFSET_MASK		0x1f