Lines Matching +full:0 +full:x720
17 #define AURORA_SYNC_REG 0x700
18 #define AURORA_RANGE_BASE_ADDR_REG 0x720
19 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
20 #define AURORA_INVAL_RANGE_REG 0x774
21 #define AURORA_CLEAN_RANGE_REG 0x7b4
22 #define AURORA_FLUSH_RANGE_REG 0x7f4
26 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
28 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
37 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
39 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
41 (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
47 #define AURORA_ERR_CNT_REG 0x600
48 #define AURORA_ERR_ATTR_CAP_REG 0x608
49 #define AURORA_ERR_ADDR_CAP_REG 0x60c
50 #define AURORA_ERR_WAY_CAP_REG 0x610
51 #define AURORA_ERR_INJECT_CTL_REG 0x614
52 #define AURORA_ERR_INJECT_MASK_REG 0x618
56 (0x1 << AURORA_ERR_CNT_CLR_OFFSET)
59 (0x7fff << AURORA_ERR_CNT_UE_OFFSET)
60 #define AURORA_ERR_CNT_CE_OFFSET 0
62 (0xffff << AURORA_ERR_CNT_CE_OFFSET)
66 (0x7 << AURORA_ERR_ATTR_SRC_OFF)
69 (0xf << AURORA_ERR_ATTR_TXN_OFF)
72 (0x3 << AURORA_ERR_ATTR_ERR_OFF)
73 #define AURORA_ERR_ATTR_CAP_VALID_OFF 0
75 (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF)
77 #define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0
81 (0xfff << AURORA_ERR_WAY_IDX_OFF)
84 (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET)
86 #define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0
88 #define AURORA_ERR_INJECT_CTL_EN_MASK 0x3
89 #define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2
90 #define AURORA_ERR_INJECT_CTL_EN_ECC 0x1
96 #define AURORA_CTRL_FW 0x100
101 #define AURORA_CACHE_ID 0x100