Lines Matching +full:cortex +full:- +full:a8
2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
42 @ i-cache availability, branch penalties, etc.
49 @ [***] which is also ~35% better than compiler generated code. Dual-
50 @ issue Cortex A8 core was measured to process input block in
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
56 @ Cortex A8 core and in absolute terms ~870 cycles per input block
61 @ Profiler-assisted and platform-specific optimization resulted in 10%
62 @ improvement on Cortex A8 core and 12.2 cycles per byte.
70 stmdb sp!,{r4-r12,lr}
104 str r9,[r14,#-4]!
129 str r9,[r14,#-4]!
154 str r9,[r14,#-4]!
179 str r9,[r14,#-4]!
204 str r9,[r14,#-4]!
232 str r9,[r14,#-4]!
245 str r9,[r14,#-4]!
262 str r9,[r14,#-4]!
279 str r9,[r14,#-4]!
296 str r9,[r14,#-4]!
317 str r9,[r14,#-4]!
333 str r9,[r14,#-4]!
349 str r9,[r14,#-4]!
365 str r9,[r14,#-4]!
381 str r9,[r14,#-4]!
406 str r9,[r14,#-4]!
423 str r9,[r14,#-4]!
440 str r9,[r14,#-4]!
457 str r9,[r14,#-4]!
474 str r9,[r14,#-4]!
499 ldmia sp!,{r4-r12,pc}