Lines Matching +full:versatile +full:- +full:sysreg
1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a5";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a5";
49 next-level-cache = <&L2>;
58 reserved-memory {
59 #address-cells = <1>;
60 #size-cells = <1>;
66 compatible = "shared-dma-pool";
68 no-map;
77 clock-names = "pxlclk";
80 memory-controller@2a150000 {
84 clock-names = "apb_pclk";
87 memory-controller@2a190000 {
93 clock-names = "apb_pclk";
97 compatible = "arm,cortex-a5-scu";
102 compatible = "arm,cortex-a5-twd-timer";
108 compatible = "arm,cortex-a5-global-timer",
109 "arm,cortex-a9-global-timer";
116 compatible = "arm,cortex-a5-twd-wdt";
121 gic: interrupt-controller@2c001000 {
122 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
123 #interrupt-cells = <3>;
124 #address-cells = <0>;
125 interrupt-controller;
130 L2: cache-controller@2c0f0000 {
131 compatible = "arm,pl310-cache";
134 cache-level = <2>;
138 compatible = "arm,cortex-a5-pmu";
144 compatible = "arm,vexpress,config-bus";
145 arm,vexpress,config-bridge = <&v2m_sysreg>;
149 compatible = "arm,vexpress-osc";
150 arm,vexpress-sysreg,func = <1 0>;
151 freq-range = <50000000 100000000>;
152 #clock-cells = <0>;
153 clock-output-names = "oscclk0";
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 1>;
160 freq-range = <5000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk1";
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 2>;
169 freq-range = <80000000 120000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk2";
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 3>;
178 freq-range = <23750000 165000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk3";
185 compatible = "arm,vexpress-osc";
186 arm,vexpress-sysreg,func = <1 4>;
187 freq-range = <80000000 80000000>;
188 #clock-cells = <0>;
189 clock-output-names = "oscclk4";
194 compatible = "arm,vexpress-osc";
195 arm,vexpress-sysreg,func = <1 5>;
196 freq-range = <25000000 60000000>;
197 #clock-cells = <0>;
198 clock-output-names = "oscclk5";
201 temp-dcc {
203 compatible = "arm,vexpress-temp";
204 arm,vexpress-sysreg,func = <4 0>;
210 compatible = "simple-bus";
212 #address-cells = <2>;
213 #size-cells = <1>;
221 #interrupt-cells = <1>;
222 interrupt-map-mask = <0 0 63>;
223 interrupt-map = <0 0 0 &gic 0 0 4>,
269 compatible = "simple-bus";
270 #address-cells = <1>;
271 #size-cells = <1>;
273 #interrupt-cells = <1>;
274 interrupt-map-mask = <0 3>;
275 interrupt-map = <0 0 &gic 0 36 4>,